Category Archives: 20nm

Paul McLellan on 20nm design

EDA analyst and SemiWiki writer Paul McLellan published an article on 20nm design last week. It’s based on the Cadence White Paper on the same topic. You can see Paul’s article here. The Cadence 20nm White Paper is here. Advertisements

Posted in 20nm, EDA360, Silicon Realization | Leave a comment

5-minute, 20nm Q&A. All you need to know in 5 minutes.

What are the key advantages of moving to 20nm? There are three primary reasons why we are seeing more system and semiconductor companies consider 20nm: performance, power, and area (PPA). Essentially, this is a “next-node” answer, which is still as … Continue reading

Posted in 20nm, Silicon Realization, SoC, SoC Realization | Tagged , , , | Leave a comment

ARM, TSMC announce collaboration on FINfet-based ARM v8 processor core for sub-20nm SoC designs

Today, ARM and TSMC announced a multi-year deal to develop a 64-bit ARM v8 processor “beyond” the 20nm node using FINfets. The collaboration includes the ARMv8 architecture, ARM Artisan physical IP, and TSMC’s FinFET process technology. The target of this … Continue reading

Posted in 10nm, 14nm, 20nm, ARM, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , | Leave a comment

Friday Video: Luigi Capodieci, a fellow at GLOBALFOUNDRIES, talks 20nm and below, EUV, FINFETs, and the state of the foundry business

Be sure to watch this excellent 13-minute interview done by Mark LePedus starring Luigi Capodieci, a fellow with GLOBALFOUNDRIES, to get a close-up-and-personal look at the state of the foundry business (it’s not dying), 20nm design, EUV in the wings, … Continue reading

Posted in 14nm, 20nm, EUV, Globalfoundries, Silicon Realization | Tagged , , | Leave a comment

Daniel Nenni in SemiWiki: 20nm is like mango beer. Surprisingly, “very good!!!”

Well this is a strange analogy that would never occur to me. Daniel Nenni in his new SemiWiki post compares the 20nm process node to—of all things—mango beer. He writes: “As it turns out, the mango beer is very good! … Continue reading

Posted in 20nm, EDA360, Silicon Realization | Tagged , , , , | Leave a comment

Innovate or die! A high-tech parable from this week’s Time Magazine

Today I was reading this week’s issue of Time Magazine while eating lunch in my secret fish-and-chips restaurant at an undisclosed location in Milpitas, California when I chanced upon a fascinating article about RIM, maker of the BlackBerry. The article’s … Continue reading

Posted in 2.5D, 20nm, 28nm, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , | Leave a comment

20nm design: What have we learned so far?

Even if you are not currently considering 20nm design, you owe it to yourself to download and read a new 9-page White Paper titled “A Call to Action: How 20nm Will Change IC Design” to learn about some tectonic shifts … Continue reading

Posted in 20nm, 28nm, AMS, Analog, ARM, Design Abstraction, EDA360, Silicon Realization, Verification | Tagged , , , , , , , | 1 Comment

Want details on the TSMC 20nm process technology?

Daniel Nenni has just published a great, short overview of the specifications for the TSMC 20nm process technology on his SemiWiki site. Nenni’s report hits the important benefits of the advanced process technology right at the beginning: 30% faster 1.9x … Continue reading

Posted in 20nm, TSMC | Tagged , , , , | 1 Comment

Hear IBM’s Dr. Gary Patton on the future of silicon scaling…and beyond. (Audio from The Common Technology Platform Forum keynote)

Earlier this year, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center, spoke about the future of semiconductor scaling and beyond. It was a terrific keynote speech at the Common Platform Technology Forum and was similar to … Continue reading

Posted in 10nm, 14nm, 20nm, 3D, EDA360, IBM, Silicon Realization | Tagged , , | Leave a comment

This just out from DAC 2012: video interview with EDA bloggers Goering and Leibson on IP subsystems, 20nm, and more

Want to know what’s going to happen at DAC 2012? Oh, wait, that was a couple of weeks ago. Which is how long it took to get post this video of EDA bloggers Richard Goering and Steve Leibson from a … Continue reading

Posted in 20nm, 28nm, DAC, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , | Leave a comment

3D Thursday: My breakfast with IBM’s Gary Patton leads to a discussion of 20nm and 14nm IC design

Yesterday I moderated a panel on 2(x)nm success at DAC and one of the panelists was Dr. Gary Patton, VP of IBM’s Semiconductor Research and Development Center in East Fishkill, NY. I’ve heard Dr. Patton speak before and he knows … Continue reading

Posted in 14nm, 20nm, 28nm, Double Patterning, EDA360, EUV, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , , | Leave a comment

Beyond breakfast: An ethical bribe for attending “The Path to Yielding at 2(x)nm and Beyond” at DAC

Yesterday, I wrote about a terrific discussion panel about the challenges of 20nm design at DAC. I am moderating the panel and there will be speakers from the Common Platform partners including IBM, Samsung, GLOBALFOUNDRIES (just confirmed!), and Cadence. (See … Continue reading

Posted in 20nm, DAC, EDA360, Silicon Realization | Tagged , , , , , | Leave a comment

At DAC: The path to 20nm includes breakfast on Wednesday, June 6

Want to know how to get to 20nm? Want to know why? Want breakfast at DAC on June 6? This is indeed your lucky day because you can get it all done at a special DAC breakfast panel titled “The … Continue reading

Posted in 20nm, DAC, EDA360, Silicon Realization | Tagged , | Leave a comment

Moore’s Law: Wanted, Dead or Alive

Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held … Continue reading

Posted in 20nm, 28nm, 32nm, 40nm, 65nm, EDA360, IBM, Low Power, Memory, Multicore, Packaging, TSV | Tagged , , , , , , , | 2 Comments

At DAC, take the path to successful 20nm design. The same path leads to breakfast. Wednesday, June 6

If you’ve been following along—or even if you haven’t—Cadence held three 20nm Webinars last week. Perhaps you have to see it in person before you believe it. Fair enough. Here’s your chance to hear first-hand how you can develop high-yielding … Continue reading

Posted in 20nm, EDA360, IBM, Samsung, Silicon Realization, SoC, SoC Realization | Tagged , , , | Leave a comment

FREE Webinar on the Challenges of 20nm design. Second in a 3-part series from Cadence

The second of a series of three Cadence Webinars on 20nm design is now archived and available for viewing if you missed the live event. You can read about this Webinar in Richard Goering’s blog (“Cadence, Samsung Detail 20nm RTL-to-GDSII … Continue reading

Posted in 20nm, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , , , | Leave a comment

Are you preparing for 20nm design? This FREE On-Demand Webinar can help.

Last week ARM, TSMC, and Cadence held a Webinar on 20nm design covering three main points: Its adoption is inevitable. The design and manufacturing challenges are significant. The challenges are manageable given the right tools and methodologies, and solutions are … Continue reading

Posted in 20nm, EDA360, Silicon Realization | Tagged , , , , , | Leave a comment

3D Thursday: GLOBALFOUNDRIES adds TSV capability for 28nm and 20nm die to Fab 8 in Saratoga County, New York

Customers’ clamor for 3D IC assembly capability and die with TSVs (through-silicon vias) has apparently gotten loud enough to cause a change of game plan for GLOBALFOUNDRIES, which announced today that it is spending “tens of millions of dollars” to … Continue reading

Posted in 20nm, 28nm, 3D, EDA360, Globalfoundries, Silicon Realization, SoC, SoC Realization, TSV | Tagged , , , , , , | Leave a comment

Three free Webinars answer your questions on 20nm SoC design. What questions do you have?

What can you reasonably expect to get from 20nm? What does it take to implement an ARM Cortex-A15 processor in 20nm? What might come between you and success at 20nm? How can you be more productive when creating 20nm designs? … Continue reading

Posted in 20nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , | Leave a comment

Optimizing ARM-based advanced-node SoCs at 28nm and 20nm? Learn how to optimize for power, performance, and area on May 14 in Munich.

Physical-aware synthesis and clock-concurrent optimization are two new ways to optimize your ARM-based advanced-node or mixed-signal SoCs for power, performance, and area (PPA). CDNLive! EMEA includes a Techtorial focusing on several methods of PPA optimization for ARM-based advanced-node SoCs at … Continue reading

Posted in 20nm, 28nm, ARM, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , | Leave a comment

TSMC simplifies life at 20nm, will offer a single 20nm process technology

TSMC’s Executive Vice President and Co-Chief Operating Officer Dr. Shang-yi Chiang said at yesterday’s TSMC Symposium that the company will offer one process at the 20nm node, as reported by Dylan McGrath of EETimes. This position differs from the two- … Continue reading

Posted in 20nm, EDA360, Silicon Realization | Tagged , , | Leave a comment

Looking at 20nm design? Three free Webinars can help.

With the 20nm click on the process technology dial staring us in the face, you might be wanting some informative, experience-based help. Three free Webinars taking place on May 1, 2, and 3 will give you some extra oomph in … Continue reading

Posted in 20nm, EDA360, Silicon Realization, TSMC | Tagged , , , | Leave a comment

What are the challenges of EUV lithography and the issues surrounding double patterning? CDNLive! presentation provides details.

Richard Goering has just published an excellent blog post on double patterning for 20nm and 14nm process geometries in his blog Industry Insights. The post is based on a paper presented by IBM Distinguished Engineer Lars Liebman at the recent … Continue reading

Posted in 14nm, 20nm, Double Patterning, EDA360, EUV, Silicon Realization | Tagged , , , , , , | Leave a comment

Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm

This week at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote covering  the industry’s challenges and progress at 20nm and … Continue reading

Posted in 10nm, 14nm, 20nm, 28nm, Design Abstraction, Design Intent, DFM, Double Patterning, EDA360, IBM, Silicon Realization | Tagged , , , , , , , , | Leave a comment

Scaling the 20nm peaks to look at the 14nm cliff, Part 1: Tom Beckley from Cadence maps the challenges of advanced node design at ISQED

Yesterday at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote that lays out the challenges for IC designers tackling advanced … Continue reading

Posted in 14nm, 20nm, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , , | 1 Comment