Tag Archives: JEDEC

Friday Video: A personal invitation to Memcon from Sanjay Srivastava

Want to know why you need to be at Memcon this year? Here’s Denali Software founder Sanjay Srivastava to tell you why: Now go and sign up! It’s a free ticket and includes breakfast, lunch, and some goodies—not to mention … Continue reading

Posted in Memory, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , | Leave a comment

3D Thursday: Wide I/O and TSVs have a ripple effect on the DRAM controller. Who knew?

Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading

Posted in 2.5D, 3D, DAC, EDA360, IP, Silicon Realization, SoC, SoC Realization, System Realization, TSV, Wide I/O | Tagged , , , , , | Leave a comment

3D Thursday: Qualcomm’s Nick Yu says “3D DRAM stacking has started—it’s shipping in products”

Today’s GSA Silicon Summit held at the Computer History Museum in Mountain View, California included a talk on 3D IC assembly by Nick Yu, VP of Engineering, VLSI Engineering, at Qualcomm. Yu is in charge of Qualcomm’s technology roadmaps including … Continue reading

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Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , | Leave a comment

3D Thursday: Boosting the bandwidth of Wide I/O SDRAM to 1 Tbit/sec through standards evolution

This week’s DesignCon included a panel on 3D standards. You can read a review of the panel here in EETimes. Many topics were discussed, but the nugget I want to focus on in this blog post is the issue of … Continue reading

Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , | Leave a comment

3D Thursday: Count Renesas in with the 3D IC poker game, says Nikkei Electronics

Last week, Masahide Kimura at Nikkei Electronics in Japan published an article titled “Renesas to Commercialize TSV Technology for Wide I/O DRAM-compatible Mobile SoCs” that clearly puts Renesas in the middle of the industry’s 3D IC efforts. Reading between the … Continue reading

Posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , | Leave a comment

3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it?

For the last 3D Thursday blog post of 2011in the EDA360 Insider, I thought I’d take a flight of fancy and try to put as many of this year’s 3D IC concepts as possible together to see what we might … Continue reading

Posted in 2.5D, 3D, EDA360, Memory, SoC, SoC Realization, System Realization | Tagged , , , , , , | Leave a comment

JEDEC releases more details about DDR4 SDRAM spec. Want to know what they are?

Although DDR3 memory is just ramping up in sales, JEDEC has been working on the next-generation DDR4 specification for faster SDRAM that consumes even less power. To achieve these goals, JEDEC announced yesterday that has specified the following key features … Continue reading

Posted in EDA360, Memory, SoC Realization | Tagged , , , | 1 Comment

The DDR4 SDRAM spec and SoC design. What do we know now?

DDR4 SDRAM is coming. JEDEC may not have released the final spec yet but Samsung made the first DDR4 memory chip announcement in January of this year—a 2133MHz device built with a 30nm process technology—and Hynix followed suit in April … Continue reading

Posted in EDA360, IP, Silicon Realization, SoC Realization, System Realization, Verification | Tagged , , , , | Leave a comment

Urgent: You have only 24 hours to sign up for a free DDR4 Webinar including just-released info from the JEDEC committee

I just heard from the Cadence memory interface guru himself, Marc Greenberg, about a DDR4 Webinar he’s giving tomorrow (Thursday) during the EETimes Virtual SoC event. Here’s what Marc wrote: “I am presenting a Webinar on DDR4 tomorrow (Thursday) at … Continue reading

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