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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Friday Video: Ready for a little mobile phone teardown archaeology? Dave Jones compares state of the art in 1994 (Motorola) with an evolved 2000 (Nokia)
- 20nm design: What have we learned so far?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
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Tag Archives: Field-programmable gate array
Hot Chips 24 in August will feature a 3D tutorial plus details of new chips from AMD, Intel, Xilinx, and more
This year’s Hot Chips conference takes place on August 24-29 in a new venue: The Flint Center for the Performing Arts in Cupertino, CA. On the afternoon of August 27, there’s a die-stacking tutorial with presentations from AMD, Amkor, SK … Continue reading
Posted in EDA360
Tagged Advanced Micro Devices, AMD, Field-programmable gate array, Hot Chips, Intel, Toshiba, Xilinx
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System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang
Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading
Xilinx 28nm low-power SoC design class, part 6: Vccaux, the “other” power supply
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, Low Power, Xilinx
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Xilinx 28nm low-power SoC design class, part 5: Intelligent clock gating
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, Low Power, Xilinx
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Xilinx 28nm low-power SoC design class, part 4: Power gating RAMs
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, Xilinx
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Xilinx 28nm low-power SoC design class, part 3: Optimizing the transistor mix
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, TSMC, Xilinx
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Xilinx 28nm low-power SoC design class, part 2: Process Technology
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, TSMC, Xilinx
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