Tag Archives: Xilinx

Xilinx takes Zynq to 11—or more precisely to 1GHz

In the satirical 1984 movie “This is Spinal Tap,” Nigel the guitarist explains why the volume controls on his Marshall amps go to 11 instead of 10 like everyone else’s amps: “If we need that extra push over the cliff,” … Continue reading

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Hot Chips 24 in August will feature a 3D tutorial plus details of new chips from AMD, Intel, Xilinx, and more

This year’s Hot Chips conference takes place on August 24-29 in a new venue: The Flint Center for the Performing Arts in Cupertino, CA. On the afternoon of August 27, there’s a die-stacking tutorial with presentations from AMD, Amkor, SK … Continue reading

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3D Thursday: ARM, HP, and SK hynix join Hybrid Memory Cube Consortium (HMCC)

Add ARM, HP, and SK hynix to the growing list of companies in the Hybrid Memory Cube Consortium (HMCC). The three new members join the original founding companies, Micron and Samsung, along with Altera, IBM, Microsoft, Open-Silicon, and Xilinx plus … Continue reading

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Friday Video: EDA360 Insider talks HW/SW Codesign and Xilinx Zynq Dev Board with ChipEstimate.TV at DAC

I spent a few minutes with Sean O’Kane of ChipEstimate.TV at DAC earlier this month talking about system design, HW/SW codesign, and the new Avnet Dev Board for the Xilinx Zynq-7000 EPP. Here’s the video:

Posted in DAC, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , | Leave a comment

Can 2.5D IC assembly really reduce SoC software-development costs? Gabe Moretti thinks it can

Last week on the EDA Café Web site, EDA Editor and Industry Observer Gabe Moretti discussed my DAC blog post on Wally Rhines’ discussion of software’s role in the rising cost of SoC development. (See “Some chip-design reality from Mentor’s … Continue reading

Posted in 2.5D, 3D, EDA360, SoC, SoC Realization, System Realization | Tagged , , , , , , | Leave a comment

3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—“Learn to work together”

Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about … Continue reading

Posted in 2.5D, 3D, DAC, EDA360, Low Power, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , , , , | 5 Comments

Friday Video + 3D Thursday: Xilinx Virtex-7 H580T uses 3D assembly to merge 28Gbps xceivers, FPGA fabric

The first 3D part in the Xilinx Virtex-7 FPGA family—the 2000T—permitted the construction of a huge FPGA while sidestepping the yield issues of large 28nm die. Now, Xilinx has used 3D IC assembly to meld two FPGA logic slices and … Continue reading

Posted in 2.5D, 28nm, 3D, EDA360, FPGA, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , | Leave a comment

3D Thursday: 3D IC success stories—a DAC panel. June 7

What better way to understand the realities of 3D IC assembly than to listen to the pioneers who have already taken the arrows so you won’t have to? That’s the topic of the upcoming DAC panel: “Is 3-D Ready for … Continue reading

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Xilinx Vivado Design Suite brings SoC design style to advanced-node FPGA development

In a complete overhaul of its FPGA design tools, Xilinx has just announced the Vivado Design Suite for its current-generation 7 Series FPGAs (including the Zynq-7000 Extensible Processing Platform) and future FPGA generations. With this design-tool release, Xilinx is acknowledging … Continue reading

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Friday Video: Xilinx FPGA + 7-segment Red LED array + Eadweard Muybridge = Wow!

Keep watching. First impressions can deceive.

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Amazing Friday Video: Xilinx GTZ SerDes transceivers pump 26Gbps/channel through Luxtera silicon photonics module

Setup for this video is pretty complicated so bear with me. The following video shows a Xilinx test chip with “7 Series GTX” transceivers pumping 26Gbps data over four channels through a stand-alone Luxtera “silicon optics” multichannel transceiver module. The … Continue reading

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Friday Video: Two of this week’s EETimes ACE Award Winners related to each other: Xilinx Zynq and Cadence Virtual System Platform

This week at Design West in San Jose—the conference formerly known as the Embedded Systems Conference—EETimes gave out ACE awards to the year’s outstanding companies, people, and products. Two of the ACE winners have something in common. The first winner, … Continue reading

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Hardware/Software Codesign: Pink elephants on parade?

As part of this week’s DVCon event being held in Silicon Valley, the EDAC Emerging Companies Committee sponsored a really intense and well-attended evening panel on hardware/software codesign. The effervescent Paul McLellan moderated the panel. (If you’ve not read his book, … Continue reading

Posted in EDA360, Firmware, SoC, SoC Realization, System Realization, Virtual Prototyping | Tagged , , , , , , , | Leave a comment

3D Thursday: 40G and 100G optical Ethernet—Killer 3D app? Perhaps. Compelling? Definitely.

I’ve written several times about Wide I/O DRAM and how its speed and power advantages make it a slam dunk and killer app for 3D IC assembly. I saw another such 3D IC killer app this week at the Ethernet … Continue reading

Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , , | 5 Comments

3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work

I recently covered the groundbreaking WIOMING 3D chip design done by CEA-Imec in conjunction with ST-Ericsson. (See “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. … Continue reading

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3D Thursday: TSMC’s 3D plans and the word on 3D from Xilinx, Nvidia, IMEC, and STATS ChipPAC

For another take on last month’s RTI 3D conference held in Burlingame, CA, see Dr. Phil Garrou’s blog on the ElectroIQ site. Click here. For previous EDA360 Insider coverage of this event, see “3D Week: Wide I/O SDRAM, Network on … Continue reading

Posted in 3D, EDA360, Silicon Realization, SoC Realization, System Realization, TSMC | Tagged , , , , | Leave a comment

Friday Video: Want a demo of the Xilinx Zynq 7000 EPP virtual platform?

Don’t get the whole virtual platform thing as it applies to the new Xilinx Zynq 7000 EPP? Here’s the concise explanation and a demo in three and a half minutes from ChipEstimate.com.

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3D Thursday: Is 2.5D IC assembly “buzz-worthy”?

I’ve written several times about the Xilinx Virtex-7 2000T FPGA that uses 2.5D IC assembly techniques to form four FPGA die into one FPGA package with two million logic cells. (See “3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers … Continue reading

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3D Thursday: Who is responsible for successful 2.5D and 3D assembly? eSilicon is perhaps saying “Us”

Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: … Continue reading

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3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology

Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: … Continue reading

Posted in 2.5D, 28nm, 3D, 65nm, Silicon Realization, SoC, SoC Realization, TSV | Tagged , , , , | 2 Comments

3D Thursday: Where can you start with 3D?

My first panelist to speak on last week’s 3D IC panel at the 9th International SoC Conference in Newport Beach was Herb Reiter, generally known as “Mr. 3D.” Herb knows everyone in the industry connected to anything 3D. He’s been … Continue reading

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3D Thursday: Low-cost, all-day workshop on 3D IC to be held in Newport Beach, December 9. Early bird discount ends November 25

This has to be the 3D IC educational bargain for this year. The Orange County Chapter of the IEEE Components, Packaging and Manufacturing Technology (CPMT) Society is sponsoring an all-day workshop on 3D IC technology on December 9, 2011. The … Continue reading

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3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)

Tuesday, Xilinx announced that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, … Continue reading

Posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , | Leave a comment

Want to start writing code for the two ARM Cortex-A9 processors on the Xilinx Zynq-7000 EPP right now? Virtual Platform makes it possible

As of today, you can start to develop application software for the Xilinx Zynq-7000 family of Extensible Processing Platforms (EPP) using a virtual prototyping platform announced today and jointly developed by Xilinx and Cadence. The virtual platform provides an accurate … Continue reading

Posted in Apps, ARM, Cortex-A9, EDA360, FPGA prototyping, SoC Realization, System Realization, TLM, Virtual Prototyping | Tagged , , , , , | Leave a comment

Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)

Xilinx announced today that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, … Continue reading

Posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, TSV | Tagged , , , , , | Leave a comment