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- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- Chairman and CEO Morris Chang provides a semiconductor industry view of 28nm, 3D, and market drivers at TSMC’s Technology Day
- ISQED: Why does a trailing-edge digital IC process = a leading-edge analog IC process? TI’s Dr. Venu Menon lays bare the secrets of the analog IC business
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
- Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?
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Tag Archives: PHY
Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
Rick Merritt has just published an interesting article in EETimes: the PCI Special Interest Group (PCI SIG) expects to announce an adaptation of the ever-popular PCIe interface for mobile devices including smartphones. Merritt reports that the PCI SIG and MIPI … Continue reading
Posted in EDA360, IP, Mobile, SoC Realization, System Realization
Tagged MIPI Alliance, PCI Express, PCI SIG, PHY
2 Comments
3D Thursday: 40G and 100G optical Ethernet—Killer 3D app? Perhaps. Compelling? Definitely.
I’ve written several times about Wide I/O DRAM and how its speed and power advantages make it a slam dunk and killer app for 3D IC assembly. I saw another such 3D IC killer app this week at the Ethernet … Continue reading
Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 100 Gigabit Ethernet, 100G, 40G, AOC, Ethernet, Luxtera, MSA, PHY, Xilinx
5 Comments
Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP
In conjunction with this week’s Ethernet Technology Summit being held in San Jose, Cadence has announced commercial availability of MAC (Media Access Control), PCS (Physical Coding Sublayer) and BEAN (Backplane Ethernet Auto-Negotiation) IP blocks. The 40/100G MAC controller is fully … Continue reading
Posted in EDA360, Silicon Realization, SoC, SoC Realization
Tagged 100 Gigabit Ethernet, 100G, 40G, Ethernet, Gigabit Ethernet, Media Access Control, MII, PCS, PHY, SerDes, Verilog
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