Tag Archives: PHY

Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.

Posted on September 13, 2012 by

Rick Merritt has just published an interesting article in EETimes: the PCI Special Interest Group (PCI SIG) expects to announce an adaptation of the ever-popular PCIe interface for mobile devices including smartphones. Merritt reports that the PCI SIG and MIPI … Continue reading →

Posted in EDA360, IP, Mobile, SoC Realization, System Realization | Tagged , , , | 2 Comments

3D Thursday: 40G and 100G optical Ethernet—Killer 3D app? Perhaps. Compelling? Definitely.

Posted on February 22, 2012 by

I’ve written several times about Wide I/O DRAM and how its speed and power advantages make it a slam dunk and killer app for 3D IC assembly. I saw another such 3D IC killer app this week at the Ethernet … Continue reading →

Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , , | 5 Comments

Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP

Posted on February 21, 2012 by

In conjunction with this week’s Ethernet Technology Summit being held in San Jose, Cadence has announced commercial availability of MAC (Media Access Control), PCS (Physical Coding Sublayer) and BEAN (Backplane Ethernet Auto-Negotiation) IP blocks. The 40/100G MAC controller is fully … Continue reading →

Posted in EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , , , , , | Leave a comment