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- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
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Top Posts
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- ARM Cortex-A15—does this processor IP core need a new category…Superstar IP?
- My workbench from 1978 highlighted in EETimes as one of engineering’s messiest desks
- 3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you're not designing FPGAs!
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- ARM unveils 64-bit v8 architecture at ARM TechCon 2011
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
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Tag Archives: DDR4
Who else wants to learn high-speed PCB design and signal integrity analysis from world-renown expert Robert Hanson—for FREE?
Do the words “high-speed PCB design” make you twitch uncontrollably? How about “signal integrity analysis”? “Crosstalk”? Perhaps the phrase “complex power-delivery networks” is your nemesis. All of these topics can be real bears to deal with when you are laying … Continue reading
Posted in EDA360, Packaging, pcb
Tagged DDR3, DDR4, PDN, power distribution network, Robert Hanson, signal integrity
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Master the secrets of system design using DDR4 SDRAM
It is rare that you get to sit at the feet of a certified master and learn. If you’re interested in designing with DDR4 SDRAM, then this is your chance. On Tuesday, October 25, at ARM TechCon, Marc Greenberg will … Continue reading
What’s it take to design DDR4 into your next SoC? Newly released DFI 3.0 Spec opens the flood gates for DDR4 design
DDR4 SDRAM probably won’t be appearing until 2013 and probably won’t become the mainstream SDRAM technology until 2015 (updated estimates from “Memory to processors: “Without me, you’re nothing.” DDR4 is on the way.”) but the new DFI 3.0 preliminary specification … Continue reading
Posted in EDA360, Memory, Silicon Realization, SoC Realization
Tagged DDR4, DFI, SDRAM
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How can you be sure DDR2, DDR3, and DDR4 SDRAMs will work properly in your system?
LeCroy introduced an upgrade to its Kibra 380 DDR3 SDRAM protocol analyzer today. The analyzer’s probes plug in series with the DDR3 SDRAM modules and the analyzer can identify more than 65 JEDEC command protocol and timing violations in real … Continue reading
Posted in EDA360, Silicon Realization, SoC Realization, System Realization, Verification
Tagged DDR2, DDR3, DDR4, IDF, Intel Developer Forum
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JEDEC releases more details about DDR4 SDRAM spec. Want to know what they are?
Although DDR3 memory is just ramping up in sales, JEDEC has been working on the next-generation DDR4 specification for faster SDRAM that consumes even less power. To achieve these goals, JEDEC announced yesterday that has specified the following key features … Continue reading
Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?
Last week, I quoted Ann Steffora Mutschler’s article about the information that Micron has revealed about it’s 3D Hybrid Memory Cube. Now that I’ve got the paper Micron presented at last week’s Hot Chips 23 conference, I’d like to explain … Continue reading
Friday Video: What’s Next For Memory Designs In 2012? – from Agilent
Agilent has created a 6-part video series titled “What’s Next For Memory Designs In 2012?” that’s well worth a look. There’s about 30 minutes of video total, chopped into 2-8 minute pieces that you’ll want to watch if you have any … Continue reading
The DDR4 SDRAM spec and SoC design. What do we know now?
DDR4 SDRAM is coming. JEDEC may not have released the final spec yet but Samsung made the first DDR4 memory chip announcement in January of this year—a 2133MHz device built with a 30nm process technology—and Hynix followed suit in April … Continue reading
Posted in EDA360, IP, Silicon Realization, SoC Realization, System Realization, Verification
Tagged DDR4, DIMM, JEDEC, SDRAM, Synchronous dynamic random access memory
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Urgent: You have only 24 hours to sign up for a free DDR4 Webinar including just-released info from the JEDEC committee
I just heard from the Cadence memory interface guru himself, Marc Greenberg, about a DDR4 Webinar he’s giving tomorrow (Thursday) during the EETimes Virtual SoC event. Here’s what Marc wrote: “I am presenting a Webinar on DDR4 tomorrow (Thursday) at … Continue reading
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