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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- ARM unveils 64-bit v8 architecture at ARM TechCon 2011
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
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Tag Archives: 28nm
Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm
This week at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote covering the industry’s challenges and progress at 20nm and … Continue reading
Posted in 10nm, 14nm, 20nm, 28nm, Design Abstraction, Design Intent, DFM, Double Patterning, EDA360, IBM, Silicon Realization
Tagged 10nm, 14nm, 20nm, 28nm, extraction, FinFET, ISQED, layout, parasitic
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Want to know what’s going to happen at 20nm, 14nm, and beyond? A few answers from Frank Leu of Cadence
Last week at the Global Technology Forum held at the Santa Clara Convention Center in Silicon Valley, Cadence VP of R&D Frank Leu discussed the things we’ve learned about 20nm IC manufacturing, what we are learning about 14nm, and where … Continue reading
Posted in 14nm, 20nm, 28nm, EDA360, Globalfoundries, Samsung, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 14nm, 20nm, 28nm, Cadence, IBM, In-Design, Samsung
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By the numbers: 20nm (and 40nm, 32nm, 28nm, and 14nm) design to be discussed in technical detail at next week’s CDNLive! conference in Silicon Valley
There’s still time to register for CDNLive!, which is being held on March 13 and 14 at the Doubletree Hotel in San Jose, California so let me give you a few numbers to whet your appetite: 40nm, 32nm, 28nm, 20nm, … Continue reading
Posted in 14nm, 20nm, 28nm, 32nm, 40nm, CDNLive!, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 14nm, 20nm, 28nm, 32nm, 40nm, CDNLive!, Double Patterning, Doubletree, GlobalFoundries, IBM, Samsung
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Friday Video: Common Platform Technology Forum reveals program agenda, rolls into Silicon Valley on March 14
The Common Platform partners are IBM, Samsung, and GLOBALFOUNDRIES and their annual Technology Forum rolls into Silicon Valley on March 14, so you have a couple of weeks to sign up. This short video from ChipEstimate.com gives you a good … Continue reading
Posted in 14nm, 20nm, 28nm
Tagged 14nm, 20nm, 28nm, Common Platform, GlobalFoundries, IBM, Samsung
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Where is the mainstream IC process technology today? 28nm? 40nm? 65nm?
EDA companies like Cadence focus on developing the latest tools for bleeding-edge process technologies—28nm and 20nm today—and that’s been the emphasis of my blog posts from last week’s Global technology Conference (GTC). However, there was one panel at the conference … Continue reading
Posted in EDA360, Globalfoundries, Silicon Realization
Tagged 130nm, 180nm, 20nm, 28nm, 32nm, 40nm, 65nm, 90nm
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GLOBALFOUNDRIES’ 28nm process comes in three flavors. Which is right for you?
This week at the Global Technology conference sponsored by GLOBALFOUNDRIES and its partners, Gregg Bartlett, Senior VP of Technology and Engineering at GLOBALFOUNDRIES, discussed the three flavors of the foundry’s 28nm IC manufacturing process. The 28nm-HPP (high-performance plus) process is … Continue reading
Want to know the three lessons for GLOBALFOUNDRIES from its 28nm high-K, metal-gate development?
Yesterday, I attended the Global Technology Conference, a chip-making extravaganza underwritten by GLOBALFOUNDRIES and its partners. Got several blog posts to write about this information-packed day but thought I’d start with the three lessons that GLOBALFOUNDRIES learned from its 28nm … Continue reading
Who else wants to see a 60x speedup in DFM signoff on a 28nm design?
Rambus has announced that it achieved a 60x speedup in DRC for an IP design targeting a 28nm process technology using GLOBALFOUNDRIES’ DRC+ methodology. This approach to DRC is interesting because it’s the industry’s first approach to DRC that teams … Continue reading
Posted in EDA360, Globalfoundries, Silicon Realization
Tagged 28nm, 32nm, Design rule checking, DRC, IP, Rambus
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Are you on a Silicon Realization team? Designing ASICs and SoCs? Then you need to attend one of the Global Technology Conferences
If you’re actively developing ASICs and SoCs, you’re in the Silicon Realization business and that means you need to gather all the information you can about the business wherever you can. Globalfoundries wants to make that task easier by inviting … Continue reading
Samsung 20nm test chip includes ARM Cortex-M0 processor core. How many will fit on the head of a pin?
Samsung and Cadence just announced the successful tapeout of a 20nm logic test chip that includes the ARM Cortex-M0 microprocessor core. This announcement is yet more evidence that Moore’s Law is alive and kicking…even below 28nm. This test chip design … Continue reading
Posted in ARM, EDA360, Silicon Realization
Tagged 20nm, 28nm, ARM architecture, Cortex-M0, M0, Thumb, Thumb-2
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6-Part series of blog posts on 28nm low-power design
Over the past week, I’ve published a 6-part series of blog posts based on the Xilinx White Paper describing how the company developed the low-power aspects of its Series-7 FPGA families. The lessons apply to any team developing ASICs and … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization
Tagged 28nm, FPGA, Low Power, process technology, Xilinx
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20nm or free lunch on Monday at DAC? How about both?
Late, late notice. I know. Mea culpa. But you’ll forgive me when you hear what’s in store for you at DAC on Monday. Cadence is organizing a panel on 20nm technology that includes lunch. How cool is that? The panelists … Continue reading
Is 28nm really here? Now? When?
Last week at the Gartner Semiconductor Briefing held at the Doubletree Hotel in San Jose, Gartner Research Director Sam Wang presented a forecast for the way new IC process technologies will diffuse into the manufacturing mix. The chart he presented … Continue reading
Posted in EDA360, Silicon Realization
Tagged 20nm, 28nm, 40nm, 65nm, Foundry, Gartner, TSMC
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Gartner’s Sam Wang tosses down the 28nm Silicon Realization gauntlet to IC design houses
Sam Wang may have been a Gartner analyst for only six months or so, but he’s already learned how to drop a stunner on the audience. The event was today’s Gartner Semiconductor briefing at the San Jose Doubletree Hotel near … Continue reading
Posted in EDA360, Silicon Realization, SoC Realization
Tagged 20nm, 28nm, Foundry, Gartner, GlobalFoundries, TSMC
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Check your system-level design assumptions at the door
Jon McDonald’s opinion piece, just published in the System-Level Design Community section of Chip Design Magazine’s site, is about assumptions built into the design of complex electronic systems. Although it’s not McDonald’s topic, his writing drove my thinking along another … Continue reading
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