Where is the mainstream IC process technology today? 28nm? 40nm? 65nm?

EDA companies like Cadence focus on developing the latest tools for bleeding-edge process technologies—28nm and 20nm today—and that’s been the emphasis of my blog posts from last week’s Global technology Conference (GTC). However, there was one panel at the conference on the “mainstream revolution” in process technology. I wasn’t able to attend that panel, but Richard Goering did and you can see his account of the discussion here. I will summarize some of the points from the panel in this blog post, but first I refer you back to a blog post I wrote back in May titled “Is 28nm really here? Now? When?”. In that post, I discussed a Gartner Semiconductor Briefing held that month in San Jose and I presented this chart from Gartner on foundry capacity by process technology:

From this chart, you can see Gartner’s prediction that 28nm chips won’t be more than 10% of total worldwide foundry production by the year 2014 and that 20nm production won’t be discernable by then. The chart doesn’t show that there will also be a lot of Silicon Realization activity getting chip designs ready for the foundry during this time; the chart is only focused on production of chips that are already designed.

The GTC panel on mainstream process technology provides another view of the same situation so it’s interesting to see how these two views correlate. In the panel, there was a lot of discussion about the 65nm node being the “workhorse” process technology today and the Gartner graph indeed shows increasing production of 65nm chips. Some of the interesting 65nm quotes from the panel include:

“65nm is the workhorse.”

“65nm pays the bills as much as 28nm and 20nm”

“We respect that 65nm is the mainstream node.”

“A lot of our new designs are ramping at 65nm.”

(Note: I’m not attributing the quotes. Go read Richard’s blog to see who said what.)

In addition, older process technology nodes still have a place, especially in foundries that aren’t (yet) trying to be leading-edge chip foundries:

“I recently visited 10 different fabs in China and some haven’t made it to 65nm or even 90nm.”

So if you looked at the above Gartner chart back in that May blog post and wondered where all of those half-micron, third-micron, and quarter-micron chips might be coming from, now you know. The Gartner chart shows that more than half of the worldwide foundry capacity will still be devoted to process technologies of 130nm or older by 2014.

Why do these older nodes hang on?

“With older technologies, masks are quite cheap.”

And we are teaching old dogs new tricks (please pardon the analogy) to extend the lives of these older, less expensive process nodes:

“Now we’re putting power management back into 180nm.”

There is benefit to having EDA companies pushing the process node envelope at 28nm and 20nm, however”

“Innovation at the leading nodes is going to drive benefits back into EDA tools, IC processes, and design techniques” said Vishal Kapoor of Cadence. Following 28nm IP development, “as we waterfall back to 40nm and 65nm, we find we have better IP.”

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Globalfoundries, Silicon Realization and tagged , , , , , , , . Bookmark the permalink.

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