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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- ARM drops Cortex-A7 core on unsuspecting market, devastates low-power SoC and application-processor landscapes. What’s it all mean?
- 3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?
- Microprocessor Report publishes extremely interesting comparison of STMicroelectronics SPEAr-1300 and Xilinx Zynq ARM-based, dual core application processors
- ARM adds ARM Cortex-A15 and Cortex-R5 models to Fast Models 6.1 release, making these cores immediately available to System Realization teams
- 3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology
- Friday Video: Ready for a little mobile phone teardown archaeology? Dave Jones compares state of the art in 1994 (Motorola) with an evolved 2000 (Nokia)
- Want details on the TSMC 20nm process technology?
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Tag Archives: ASIC
High-level synthesis, C versus assembly code, and Leibson’s Law
Years ago, when I was Editor-in-Chief of EDN Magazine, I coined (but did not name) Leibson’s Law: “It takes 10 years for any disruptive technology to become pervasive in the design community.” I was reminded of that observation while reading … Continue reading
Posted in Design Abstraction, EDA360, SoC, SoC Realization, System Realization, SystemC
Tagged ASIC, High-level synthesis, LinkedIn, SoC, SystemC
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There are more than 79,997 ways for your low-power design to fail. Want to learn how to avoid a nasty surprise? For free?
There are a range of low-power design approaches for ASIC design including: Clock Gating Multi-Voltage Power Shutoff Dynamic Voltage Body Bias Adaptive Voltage All of the above Used in combination, there are more than 80,000 possible low-power modes that all … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC, SoC Realization
Tagged ASIC, Low Power, verification
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System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang
Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading
The value of IP Subsystems for ASIC and SoC Realization teams—Richard Goering interviews ChipEstimate’s Adam Traidman
Richard Goering recently interviewed the founder of ChipEstimate.com, Adam Traidman, in his Industry Insights blog and covered a range of IP topics. I found Adam’s take on IP Subsystems particularly interesting: “In my mind an IP subsystem is a set … Continue reading
Posted in EDA360, IP, SoC, SoC Realization, System Realization
Tagged ASIC, ChipEstimate, IP, SoC, Subsystems
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Power-intent methodologies: Can’t we all just get along?
All ASIC and SoC designs are low-power designs at or below the 45nm node. For that reason alone, the industry has seen the rise of power-intent descriptions to help SoC and Silicon Realization teams develop new chip designs. For the … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC, SoC Realization
Tagged ASIC, CPF, IEEE 1801, Silicon Realization, SoC, System-on-a-chip, UPF
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Free Webinar on December 8: Mixed-signal and low-power analysis and verification techniques
As the size and complexity of mixed-signal designs have grown, so has the verification task. Designers face the challenging task of verifying complex power, performance, and functionality specifications as well as validating analog and digital interactions over a broad range … Continue reading
Posted in AMS, EDA360, Silicon Realization, SoC, Verification
Tagged Analog, ASIC, Low Power, Mixed Signal
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Who else wants to overcome power-related IR-drop and electromigration challenges in mixed-signal ASIC designs?
How many times have you discovered unanticipated IR drop or electromigration problems in the power grids of your complex analog or mixed-signal ASIC? How easy was it to fix these problems? Virtually all modern IC and SoC designs include mixed … Continue reading
Posted in EDA360, Silicon Realization
Tagged Analog, ASIC, electromigration, IR drop, Mixed Signal
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Triad Semi brews potent analog/digital/ARM-processor mixes with its via-programmable arrays
Real System Realization involves the delicate balancing of many factors including performance, power, and cost. Each of these factors consists of many subcomponents. For example, most performance requirements have mixed-signal aspects and include both digital and analog components. Triad Semiconductor … Continue reading
Posted in EDA360, Silicon Realization, SoC Realization, System Realization
Tagged Analog, ASIC, gate array, Triad, Triad Semiconductor
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Agilent isn’t the only vendor differentiating its scopes with ASICs. Add Tektronix and LeCroy to the list.
Back in February, I wrote about the new Agilent InfiniiVision 2000 and 3000 X-Series of low-end, digital sampling oscilloscopes (DSOs) and mixed-signal oscilloscopes (MSOs). (See “Agilent knocks one out of the park with new, low-cost line of digital scopes—a very … Continue reading
Posted in Apps, EDA360, Silicon Realization, SoC Realization, System Realization
Tagged Agilent, ASIC, DSO, LeCroy, MSO, New Electronics, Tektronix
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Semico reports that ASICS, ASSPs, SoCs, and core-based ICs comprise the fastest growing category in MOS logic chips
EDA360 Insider followers will not be surprised to hear that Semico’s latest blog entry on Semico Spin claims that “Special Purpose Logic”—consisting of ASICS, ASSPs, SoCs, and core-based ICs—is now the fastest growing category for MOS logic chips and has … Continue reading
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