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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud
- 3D IC
- ARM architecture
- ARM Cortex-A15
- Dave Jones
- Double Patterning
- Field-programmable gate array
- Flash memory
- Freescale Semiconductor
- Jim Hogan
- Low Power
- Mixed Signal
- Multi-core processor
- Printed circuit board
- Texas Instruments
- Wide I/O
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- Xilinx Zynq EPPs based on two ARM Cortex-A9s create a new category that fits in among SoCs, FPGAs, and microcontrollers
- 3D Thursday: Intel Penwell SoC for mobile phones employs POP (package-on-package) LPDDR2 SDRAM to reduce power
- 3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you're not designing FPGAs!
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- ARM big.LITTLE multicore IP architecture wins a Microprocessor Report Analysts’ Choice Award
- The WORD on ARM’s big.LITTLE Cortex-A15/A7 design philosophy from Jack Ganssle, a leading expert and consultant on embedded design and firmware development
- Learn to use AI in design work after a great slice of Costco pizza. The talk is free. Pizza: $2
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
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Tag Archives: ASIC
There are more than 79,997 ways for your low-power design to fail. Want to learn how to avoid a nasty surprise? For free?
There are a range of low-power design approaches for ASIC design including: Clock Gating Multi-Voltage Power Shutoff Dynamic Voltage Body Bias Adaptive Voltage All of the above Used in combination, there are more than 80,000 possible low-power modes that all … Continue reading
System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang
Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading
The value of IP Subsystems for ASIC and SoC Realization teams—Richard Goering interviews ChipEstimate’s Adam Traidman
Richard Goering recently interviewed the founder of ChipEstimate.com, Adam Traidman, in his Industry Insights blog and covered a range of IP topics. I found Adam’s take on IP Subsystems particularly interesting: “In my mind an IP subsystem is a set … Continue reading
All ASIC and SoC designs are low-power designs at or below the 45nm node. For that reason alone, the industry has seen the rise of power-intent descriptions to help SoC and Silicon Realization teams develop new chip designs. For the … Continue reading
As the size and complexity of mixed-signal designs have grown, so has the verification task. Designers face the challenging task of verifying complex power, performance, and functionality specifications as well as validating analog and digital interactions over a broad range … Continue reading
Who else wants to overcome power-related IR-drop and electromigration challenges in mixed-signal ASIC designs?
How many times have you discovered unanticipated IR drop or electromigration problems in the power grids of your complex analog or mixed-signal ASIC? How easy was it to fix these problems? Virtually all modern IC and SoC designs include mixed … Continue reading
Real System Realization involves the delicate balancing of many factors including performance, power, and cost. Each of these factors consists of many subcomponents. For example, most performance requirements have mixed-signal aspects and include both digital and analog components. Triad Semiconductor … Continue reading
Agilent isn’t the only vendor differentiating its scopes with ASICs. Add Tektronix and LeCroy to the list.
Back in February, I wrote about the new Agilent InfiniiVision 2000 and 3000 X-Series of low-end, digital sampling oscilloscopes (DSOs) and mixed-signal oscilloscopes (MSOs). (See “Agilent knocks one out of the park with new, low-cost line of digital scopes—a very … Continue reading
Semico reports that ASICS, ASSPs, SoCs, and core-based ICs comprise the fastest growing category in MOS logic chips
EDA360 Insider followers will not be surprised to hear that Semico’s latest blog entry on Semico Spin claims that “Special Purpose Logic”—consisting of ASICS, ASSPs, SoCs, and core-based ICs—is now the fastest growing category for MOS logic chips and has … Continue reading