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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- 3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet
- 3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you're not designing FPGAs!
- 3D Thursday (early): Steve’s Improbable History of 3D ICs? Six decades of 3D electronic packaging
- Friday Video: The Easter Egg in the Agilent InfiniiVision 3000 X-Series DSO
- 3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D
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Tag Archives: 20nm
What are the key advantages of moving to 20nm? There are three primary reasons why we are seeing more system and semiconductor companies consider 20nm: performance, power, and area (PPA). Essentially, this is a “next-node” answer, which is still as … Continue reading
Well this is a strange analogy that would never occur to me. Daniel Nenni in his new SemiWiki post compares the 20nm process node to—of all things—mango beer. He writes: “As it turns out, the mango beer is very good! … Continue reading
Even if you are not currently considering 20nm design, you owe it to yourself to download and read a new 9-page White Paper titled “A Call to Action: How 20nm Will Change IC Design” to learn about some tectonic shifts … Continue reading
Daniel Nenni has just published a great, short overview of the specifications for the TSMC 20nm process technology on his SemiWiki site. Nenni’s report hits the important benefits of the advanced process technology right at the beginning: 30% faster 1.9x … Continue reading
Yesterday, I wrote about a terrific discussion panel about the challenges of 20nm design at DAC. I am moderating the panel and there will be speakers from the Common Platform partners including IBM, Samsung, GLOBALFOUNDRIES (just confirmed!), and Cadence. (See … Continue reading
Want to know how to get to 20nm? Want to know why? Want breakfast at DAC on June 6? This is indeed your lucky day because you can get it all done at a special DAC breakfast panel titled “The … Continue reading
At DAC, take the path to successful 20nm design. The same path leads to breakfast. Wednesday, June 6
If you’ve been following along—or even if you haven’t—Cadence held three 20nm Webinars last week. Perhaps you have to see it in person before you believe it. Fair enough. Here’s your chance to hear first-hand how you can develop high-yielding … Continue reading
Last week ARM, TSMC, and Cadence held a Webinar on 20nm design covering three main points: Its adoption is inevitable. The design and manufacturing challenges are significant. The challenges are manageable given the right tools and methodologies, and solutions are … Continue reading
What can you reasonably expect to get from 20nm? What does it take to implement an ARM Cortex-A15 processor in 20nm? What might come between you and success at 20nm? How can you be more productive when creating 20nm designs? … Continue reading
TSMC’s Executive Vice President and Co-Chief Operating Officer Dr. Shang-yi Chiang said at yesterday’s TSMC Symposium that the company will offer one process at the 20nm node, as reported by Dylan McGrath of EETimes. This position differs from the two- … Continue reading
With the 20nm click on the process technology dial staring us in the face, you might be wanting some informative, experience-based help. Three free Webinars taking place on May 1, 2, and 3 will give you some extra oomph in … Continue reading
Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm
This week at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote covering the industry’s challenges and progress at 20nm and … Continue reading
Scaling the 20nm peaks to look at the 14nm cliff, Part 1: Tom Beckley from Cadence maps the challenges of advanced node design at ISQED
Yesterday at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote that lays out the challenges for IC designers tackling advanced … Continue reading
Want to know what’s going to happen at 20nm, 14nm, and beyond? A few answers from Frank Leu of Cadence
Last week at the Global Technology Forum held at the Santa Clara Convention Center in Silicon Valley, Cadence VP of R&D Frank Leu discussed the things we’ve learned about 20nm IC manufacturing, what we are learning about 14nm, and where … Continue reading
By the numbers: 20nm (and 40nm, 32nm, 28nm, and 14nm) design to be discussed in technical detail at next week’s CDNLive! conference in Silicon Valley
There’s still time to register for CDNLive!, which is being held on March 13 and 14 at the Doubletree Hotel in San Jose, California so let me give you a few numbers to whet your appetite: 40nm, 32nm, 28nm, 20nm, … Continue reading
Friday Video: Common Platform Technology Forum reveals program agenda, rolls into Silicon Valley on March 14
The Common Platform partners are IBM, Samsung, and GLOBALFOUNDRIES and their annual Technology Forum rolls into Silicon Valley on March 14, so you have a couple of weeks to sign up. This short video from ChipEstimate.com gives you a good … Continue reading
SanDisk shows 128Gbit, 3-level cell NAND Flash memory chip at ISSCC. Is 20nm (or 19nm) here, so soon?
I’ve just posted a blog entry in the Denali Memory Report on an important NAND Flash memory announcement by SanDisk. Please check it out. http://j.mp/A6wAju
EDA companies like Cadence focus on developing the latest tools for bleeding-edge process technologies—28nm and 20nm today—and that’s been the emphasis of my blog posts from last week’s Global technology Conference (GTC). However, there was one panel at the conference … Continue reading
GLOBALFOUNDRIES talks FinFETs, EUV, 14nm, ETSOI. Any other bleeding-edge chipmaking terms you wanted to hear?
Near the end of his Global Technology Conference presentation last week, Senior VP of Technology and R&D Gregg Bartlett jumped to the future—namely 2014 to 2015. By then, GLOBALFOUNDRIES plans to be implementing the second production phase for its 20nm … Continue reading
I’ve been discussing Gregg Bartlett’s talk at this week’s Global Technology Conference and thought I’d focus this blog post on one graphic: As I mentioned in my last post, “GLOBALFOUNDRIES’ 28nm process comes in three flavors. Which is right for you?”, … Continue reading
This week at the Global Technology conference sponsored by GLOBALFOUNDRIES and its partners, Gregg Bartlett, Senior VP of Technology and Engineering at GLOBALFOUNDRIES, discussed the three flavors of the foundry’s 28nm IC manufacturing process. The 28nm-HPP (high-performance plus) process is … Continue reading
Friday Video: Everything you wanted to know about double patterning at 20nm and below…but were afraid to ask
Dr. Lars Liebman at IBM gave a very clear talk about the need for double patterning at the 22nm and 14nm nodes while at DAC a couple of months ago. Until EUV is ready for production, which is not expected … Continue reading
A number of manufacturing issues specific to 20nm pose a challenge to developing high-quality silicon and SoCs on time and on budget. Silicon Realization at such an advanced node requires a holistic approach consisting of three critical and interrelated components: … Continue reading
Samsung 20nm test chip includes ARM Cortex-M0 processor core. How many will fit on the head of a pin?
Samsung and Cadence just announced the successful tapeout of a 20nm logic test chip that includes the ARM Cortex-M0 microprocessor core. This announcement is yet more evidence that Moore’s Law is alive and kicking…even below 28nm. This test chip design … Continue reading
Cadence sponsored a lunchtime discussion panel on 20nm design today at DAC. Veteran industry analyst Jim Handy moderated the panel and the panelists included Simon Segars, Executive Vice President and General Manager for Physical IP from ARM; Ana Hunter, Vice … Continue reading