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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
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- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- ARM unveils 64-bit v8 architecture at ARM TechCon 2011
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
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Tag Archives: Wide I/O
3D Thursday: Wide I/O and TSVs have a ripple effect on the DRAM controller. Who knew?
Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading
Posted in 2.5D, 3D, DAC, EDA360, IP, Silicon Realization, SoC, SoC Realization, System Realization, TSV, Wide I/O
Tagged DRAM, JEDEC, Marc Greenberg, Mobile device, SDRAM, Wide I/O
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3D Thursday: Qualcomm’s Nick Yu says “3D DRAM stacking has started—it’s shipping in products”
Today’s GSA Silicon Summit held at the Computer History Museum in Mountain View, California included a talk on 3D IC assembly by Nick Yu, VP of Engineering, VLSI Engineering, at Qualcomm. Yu is in charge of Qualcomm’s technology roadmaps including … Continue reading
Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged DDR SDRAM, GPU, JEDEC, SDRAM, Three-dimensional integrated circuit, Wide I/O
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3D Thursday: Is Wide I/O SDRAM free for the end user???
A recent email from Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, suggested that Wide I/O used in a 3D stack is free for the end user. In other words, there’s no incremental cost in the … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O
Tagged 3D, SDRAM, TSV, Wide I/O, Wide I/O SDRAM
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3D Thursday: Boosting the bandwidth of Wide I/O SDRAM to 1 Tbit/sec through standards evolution
This week’s DesignCon included a panel on 3D standards. You can read a review of the panel here in EETimes. Many topics were discussed, but the nugget I want to focus on in this blog post is the issue of … Continue reading
Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 2.5D, 3D, JEDEC, SDRAM, Wide I/O
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3D Thursday: Count Renesas in with the 3D IC poker game, says Nikkei Electronics
Last week, Masahide Kimura at Nikkei Electronics in Japan published an article titled “Renesas to Commercialize TSV Technology for Wide I/O DRAM-compatible Mobile SoCs” that clearly puts Renesas in the middle of the industry’s 3D IC efforts. Reading between the … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O
Tagged JEDEC, mobile phone, Renesas, SoC, Wide I/O
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3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it?
For the last 3D Thursday blog post of 2011in the EDA360 Insider, I thought I’d take a flight of fancy and try to put as many of this year’s 3D IC concepts as possible together to see what we might … Continue reading
Posted in 2.5D, 3D, EDA360, Memory, SoC, SoC Realization, System Realization
Tagged 2.5D, 3D, HMC, IBM, JEDEC, Micron, Wide I/O
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3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
Yesterday, at the RTI 3D Conference, Pascal Vivet from CEA-Leti and Vincent Guérin from ST-Ericsson unveiled a 3D IC project that represents a real Tour de Force of cutting-edge system technology. The quest starts with a key question: “What’s the … Continue reading
Posted in 3D, ARM, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 3D, Cadence, Leti, LTE, Multicore, NoC, ST Ericsson, TSV, Wide I/O
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