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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Friday Video: Ready for a little mobile phone teardown archaeology? Dave Jones compares state of the art in 1994 (Motorola) with an evolved 2000 (Nokia)
- 20nm design: What have we learned so far?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
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Category Archives: IP
Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
Rick Merritt has just published an interesting article in EETimes: the PCI Special Interest Group (PCI SIG) expects to announce an adaptation of the ever-popular PCIe interface for mobile devices including smartphones. Merritt reports that the PCI SIG and MIPI … Continue reading
Posted in EDA360, IP, Mobile, SoC Realization, System Realization
Tagged MIPI Alliance, PCI Express, PCI SIG, PHY
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How many SSDs does it take to saturate PCIe Gen 3? Would you believe 16 drives?
It’s now possible to conduct some interesting performance tests on real PCIe Gen 3 products and the video below shows you a PCIe Gen 3 RAID card talking to 16 SSDs, which is the number of drives needed to saturate … Continue reading
Posted in EDA360, IP
Tagged Disk array controller, PCI Express, RAID, Sandy Bridge, Serial ATA, Solid-state drive
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3D Thursday: Wide I/O and TSVs have a ripple effect on the DRAM controller. Who knew?
Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading
Posted in 2.5D, 3D, DAC, EDA360, IP, Silicon Realization, SoC, SoC Realization, System Realization, TSV, Wide I/O
Tagged DRAM, JEDEC, Marc Greenberg, Mobile device, SDRAM, Wide I/O
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Gary Smith proposes a 3-layer taxonomy for platform-based SoC design—Live from DAC 2012
EDA’s chief analyst Gary Smith is high on IP subsystems—big ones. Only Gary calls them platforms. Why is Smith so enthusiastic? Because, as he says, he was wrong last year in his estimates of how much it costs to develop … Continue reading
Posted in DAC, IP, SoC, SoC Realization, System Realization, Texas instruments
Tagged ARM, Armada, Design Compiler, Marvell, Nvidia, OMAP, Qualcomm, Snapdragon, Tegra
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Low-Power Design: Is the Problem Solved?
“Once upon a time, you would complain if your cell phone didn’t work on one [battery] charge,” said Qi Wang—Cadence Technical Marketing Group Director for Low-Power Solutions—during his EDPS presentation in Monterey last week. “After Apple introduced the iPhone, your … Continue reading
Posted in EDA360, IP, Low Power, Silicon Realization, SoC, SoC Realization, System Realization
Tagged CPF, Low Power, PSOC, RTL, SoC
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You have six weeks to wait for the Semico IP Summit. What will you do until then?
Use of IP in the design of SoCs has long been a fact. The very name “SoC” says that you’re using microprocessor IP at the very least. With that comes memory IP, memory controller IP, interface IP, analog IP, etc. … Continue reading
Posted in EDA360, IP, SoC Realization
Tagged Advanced Micro Devices, Cadence, GlobalFoundries, Mentor Graphics, SoC, Synopsys, TSMC
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The value of IP Subsystems for ASIC and SoC Realization teams—Richard Goering interviews ChipEstimate’s Adam Traidman
Richard Goering recently interviewed the founder of ChipEstimate.com, Adam Traidman, in his Industry Insights blog and covered a range of IP topics. I found Adam’s take on IP Subsystems particularly interesting: “In my mind an IP subsystem is a set … Continue reading
Posted in EDA360, IP, SoC, SoC Realization, System Realization
Tagged ASIC, ChipEstimate, IP, SoC, Subsystems
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Playing poker with applications processors: Can two ARM Cortex-A15 cores beat four ARM Cortex-A9 cores?
One maxim in the multicore biz is that more (processor cores) is better. Is that really true? All the time? “No” says Texas Instruments. In connection with this weeks (MWC) Mobile World Congress neing held in Barcelona, Texas instruments has … Continue reading
Semico to hold IP Ecosystem conference in Silicon Valley on May 16
Chips no longer get designed without a substantial amount of commercial IP (both design IP and verification IP) and the business is now plenty big enough to merit its own conference. So research firm Semico is holding the IMPACT conference … Continue reading
ARM big.LITTLE multicore IP architecture wins a Microprocessor Report Analysts’ Choice Award
This week in the Microprocessor Report, the Linley Group announced its Analysts’ Choice Award winners and declared the ARM big.LITTLE multicore IP architecture as the best processor IP of the year: “Designed to extend battery life by up to 70%, … Continue reading
Posted in ARM, Cortex-A15, Cortex-A7, EDA360, IP, Low Power, Packaging, Silicon Realization, SoC, SoC Realization
Tagged A15, A7, ARM, Cortex, Microprocessor Report
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Would you like some ARM Cortex-A15 resources to peruse?
Thanks to LinkedIn ARM Based Group community manager Stephan Cadene, we’ve got several pointers to useful documents describing many aspects of the ARM Cortex-A15 processor core. This is all in preparation for many discussions of the ARM Cortex-A15 processor taking … Continue reading
Posted in Android, ARM, Cortex-A15, Ecosystem, EDA360, IP, Silicon Realization, SoC, SoC Realization, System Realization
Tagged ARM architecture, Broadcom, Cortex-A15, Cortex-A5, Cortex-A8, Cortex-A9, Nvidia, Samsung, ST Ericsson, TechCon, Texas Instruments
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HDMI takes over the mobile PC market. 300M HDMI-enabled units to ship in 2014 according to In-Stat
A new report from In-Stat notes “a dramatic increase for HDMI in portable consumer devices, including HD camcorders and digital still cameras. In addition, on the PC side, HDMI’s share of mobile PCs, graphics cards, and PC monitors continued to … Continue reading
How do you break the GHz barrier with ARM Cortex-A15 processor cores? Another chance to get a leg up on your SoC Realization competitors at ARM TechCon 2011
On Tuesday, October 25, you will learn how Texas Instruments and Cadence goosed the ARM Cortex-A15 processor core into the GHz+ range using an end-to-end digital design flow that includes physical-aware logic synthesis, DFT, timing optimization, optimized CTS (clock-tree synthesis), … Continue reading
Friday Video: Gary Smith speaks at DAC 2011 about IP (very large and modifiable) and platform-based design
Earlier this year at DAC, the ever-present EDA observer John Cooley conducted a panel of experts to talk about EDA. One of the expert speakers was Gary Smith, who always has something (somethings!) interesting to say. This time, he’s talking … Continue reading
Jim Hogan coins “Jobs’ Law” and nails it to the door of System and SoC Realization
Jim “make me some money” Hogan, perhaps the most visible VC in EDA, has just published an article titled “Jobs’ Law” on the System-Level Design Community Web site where he defines Jobs’ Law (Jobs, Steve Jobs, who shakes whole industries … Continue reading
Posted in EDA360, Firmware, IP, Silicon Realization, SoC Realization, System Realization
Tagged Apple, Jim Hogan, Nvidia, Steve Jobs
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Processor Wars: NVIDIA reveals a phantom fifth ARM Cortex-A9 processor core in Kal-El mobile processor IC. Guess why it’s there?
NVIDIA has extended the path to many-core design by publishing a White Paper that reveals the existence of a fifth ARM Cortex-A9 processor core in the company’s previously discussed Kal-El mobile processor. This fifth processor core implements what the company … Continue reading
Posted in Android, ARM, EDA360, Honeycomb, IP, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Dennard Scaling, DVFS, Kal-El, Moore's law, Nvidia
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What do you need to know about IP for SoC Realization?
Ron Collett, the IC industry’s most experienced ASIC and SoC project actuary—CEO of Numetrics and the man who first recognized and named the “Design Productivity Gap” —has just published an interesting essay on IP reuse in EETimes titled “The realities … Continue reading
Posted in EDA360, IP, SoC Realization
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Friday Video: IP use and abuse. Recent DAC panel discusses the ins and outs of global IP use
Adam Traidman, General Manager of ChipEstimate.com, moderated a DAC Pavilion panel on semiconductor IP use and video from that panel is now up. According to research cited by Traidman, IP use on an average SoC design has gone from 19% … Continue reading
Posted in EDA360, IP, SoC Realization
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Detailed analysis of the Cadence PCIe Gen 3 IP and VIP launch from SemiWiki’s Eric Esteve
A bit of analysis and a little history goes a long way to fleshing out the product announcement of Cadence’s PCIe Gen 3 IP and VIP offerings. This just-published analysis by SemiWiki’s Eric Esteve provides both.
Posted in EDA360, IP, SoC Realization, Verification
Tagged PCIe, PCIe Gen 3, PCIe Gen3
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Cadence and TSMC collaborate on SoC IP development, produce complete USB IP package
Working together with TSMC under the TSMC Open Innovation Platform initiative, Cadence has just introduced a certified USB 2.0/3.0 PHY/PCS/controller design IP package to support the wildly popular, advanced USB interface ports for ongoing SoC development using advanced process nodes. TSMC … Continue reading
The DDR4 SDRAM spec and SoC design. What do we know now?
DDR4 SDRAM is coming. JEDEC may not have released the final spec yet but Samsung made the first DDR4 memory chip announcement in January of this year—a 2133MHz device built with a 30nm process technology—and Hynix followed suit in April … Continue reading
Posted in EDA360, IP, Silicon Realization, SoC Realization, System Realization, Verification
Tagged DDR4, DIMM, JEDEC, SDRAM, Synchronous dynamic random access memory
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Jim Hogan details his views of SoC opportunities and again reveals his SoC Realization investment shopping list
Jim Hogan gave the keynote at today’s EETimes Virtual SoC event and he presented a deep dive into the opportunities in semiconductor device development and the associated EDA opportunities from the perspective of an investor who makes his money building, … Continue reading
Urgent: You have only 24 hours to sign up for a free DDR4 Webinar including just-released info from the JEDEC committee
I just heard from the Cadence memory interface guru himself, Marc Greenberg, about a DDR4 Webinar he’s giving tomorrow (Thursday) during the EETimes Virtual SoC event. Here’s what Marc wrote: “I am presenting a Webinar on DDR4 tomorrow (Thursday) at … Continue reading
SoC Realization White Paper from Atrenta puts it down in black and white
You owe it to yourself to read Atrenta’s new SoC Realization White Paper. At 19 pages, you’ll need about half an hour to get through it, but if you and your company are at all involved in SoC development, then … Continue reading
Posted in Apps, EDA360, IP, Silicon Realization, SoC Realization, System Realization
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