Search EDA360 Insider
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud2.5D 3D 3D IC 20nm 28nm 32nm 40nm Agilent Altera AMD Analog Android Apple ARM ARM architecture ARM Cortex-A15 ASIC Broadcom Cadence Canon Cortex Cortex-A15 Cortex-M0 DAC Dave Jones DDR3 DDR4 Double Patterning EDA EDPS Field-programmable gate array FinFET Flash Flash memory FPGA Freescale Freescale Semiconductor GlobalFoundries Google IBM Intel IP iPad iPhone JEDEC Jim Hogan Kinect Linux Low Power Lytro microcontroller Micron Microsoft Mixed Signal Multi-core processor Nvidia OrCAD pcb Printed circuit board Qualcomm Robot Samsung SDRAM Snapdragon SoC STMicroelectronics SystemC Texas Instruments TI TSMC USB verification video Wide I/O Xilinx
- GLOBALFOUNDRIES’ 28nm process comes in three flavors. Which is right for you?
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D
- What can you do with 45nm SOI? A lot, it turns out
- The WORD on ARM’s big.LITTLE Cortex-A15/A7 design philosophy from Jack Ganssle, a leading expert and consultant on embedded design and firmware development
- How do virtual prototyping, emulation, and FPGA prototyping differ? Answers from Frank Schirrmeister
- There’s a solar eclipse coming. Here’s a test shot from a Canon 60D dSLR, a Spiratone 400mm Sharpshooter, and a 2x telextender.
- Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu
Download the EDA360 Vision Paper here:
Category Archives: IP
Rick Merritt has just published an interesting article in EETimes: the PCI Special Interest Group (PCI SIG) expects to announce an adaptation of the ever-popular PCIe interface for mobile devices including smartphones. Merritt reports that the PCI SIG and MIPI … Continue reading
It’s now possible to conduct some interesting performance tests on real PCIe Gen 3 products and the video below shows you a PCIe Gen 3 RAID card talking to 16 SSDs, which is the number of drives needed to saturate … Continue reading
Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading
EDA’s chief analyst Gary Smith is high on IP subsystems—big ones. Only Gary calls them platforms. Why is Smith so enthusiastic? Because, as he says, he was wrong last year in his estimates of how much it costs to develop … Continue reading
“Once upon a time, you would complain if your cell phone didn’t work on one [battery] charge,” said Qi Wang—Cadence Technical Marketing Group Director for Low-Power Solutions—during his EDPS presentation in Monterey last week. “After Apple introduced the iPhone, your … Continue reading
Use of IP in the design of SoCs has long been a fact. The very name “SoC” says that you’re using microprocessor IP at the very least. With that comes memory IP, memory controller IP, interface IP, analog IP, etc. … Continue reading
The value of IP Subsystems for ASIC and SoC Realization teams—Richard Goering interviews ChipEstimate’s Adam Traidman
Richard Goering recently interviewed the founder of ChipEstimate.com, Adam Traidman, in his Industry Insights blog and covered a range of IP topics. I found Adam’s take on IP Subsystems particularly interesting: “In my mind an IP subsystem is a set … Continue reading
Playing poker with applications processors: Can two ARM Cortex-A15 cores beat four ARM Cortex-A9 cores?
One maxim in the multicore biz is that more (processor cores) is better. Is that really true? All the time? “No” says Texas Instruments. In connection with this weeks (MWC) Mobile World Congress neing held in Barcelona, Texas instruments has … Continue reading
Chips no longer get designed without a substantial amount of commercial IP (both design IP and verification IP) and the business is now plenty big enough to merit its own conference. So research firm Semico is holding the IMPACT conference … Continue reading
This week in the Microprocessor Report, the Linley Group announced its Analysts’ Choice Award winners and declared the ARM big.LITTLE multicore IP architecture as the best processor IP of the year: “Designed to extend battery life by up to 70%, … Continue reading
Thanks to LinkedIn ARM Based Group community manager Stephan Cadene, we’ve got several pointers to useful documents describing many aspects of the ARM Cortex-A15 processor core. This is all in preparation for many discussions of the ARM Cortex-A15 processor taking … Continue reading
A new report from In-Stat notes “a dramatic increase for HDMI in portable consumer devices, including HD camcorders and digital still cameras. In addition, on the PC side, HDMI’s share of mobile PCs, graphics cards, and PC monitors continued to … Continue reading
How do you break the GHz barrier with ARM Cortex-A15 processor cores? Another chance to get a leg up on your SoC Realization competitors at ARM TechCon 2011
On Tuesday, October 25, you will learn how Texas Instruments and Cadence goosed the ARM Cortex-A15 processor core into the GHz+ range using an end-to-end digital design flow that includes physical-aware logic synthesis, DFT, timing optimization, optimized CTS (clock-tree synthesis), … Continue reading
Friday Video: Gary Smith speaks at DAC 2011 about IP (very large and modifiable) and platform-based design
Earlier this year at DAC, the ever-present EDA observer John Cooley conducted a panel of experts to talk about EDA. One of the expert speakers was Gary Smith, who always has something (somethings!) interesting to say. This time, he’s talking … Continue reading
Jim “make me some money” Hogan, perhaps the most visible VC in EDA, has just published an article titled “Jobs’ Law” on the System-Level Design Community Web site where he defines Jobs’ Law (Jobs, Steve Jobs, who shakes whole industries … Continue reading
Processor Wars: NVIDIA reveals a phantom fifth ARM Cortex-A9 processor core in Kal-El mobile processor IC. Guess why it’s there?
NVIDIA has extended the path to many-core design by publishing a White Paper that reveals the existence of a fifth ARM Cortex-A9 processor core in the company’s previously discussed Kal-El mobile processor. This fifth processor core implements what the company … Continue reading
Ron Collett, the IC industry’s most experienced ASIC and SoC project actuary—CEO of Numetrics and the man who first recognized and named the “Design Productivity Gap” —has just published an interesting essay on IP reuse in EETimes titled “The realities … Continue reading
Adam Traidman, General Manager of ChipEstimate.com, moderated a DAC Pavilion panel on semiconductor IP use and video from that panel is now up. According to research cited by Traidman, IP use on an average SoC design has gone from 19% … Continue reading
A bit of analysis and a little history goes a long way to fleshing out the product announcement of Cadence’s PCIe Gen 3 IP and VIP offerings. This just-published analysis by SemiWiki’s Eric Esteve provides both.
Working together with TSMC under the TSMC Open Innovation Platform initiative, Cadence has just introduced a certified USB 2.0/3.0 PHY/PCS/controller design IP package to support the wildly popular, advanced USB interface ports for ongoing SoC development using advanced process nodes. TSMC … Continue reading
DDR4 SDRAM is coming. JEDEC may not have released the final spec yet but Samsung made the first DDR4 memory chip announcement in January of this year—a 2133MHz device built with a 30nm process technology—and Hynix followed suit in April … Continue reading
Jim Hogan details his views of SoC opportunities and again reveals his SoC Realization investment shopping list
Jim Hogan gave the keynote at today’s EETimes Virtual SoC event and he presented a deep dive into the opportunities in semiconductor device development and the associated EDA opportunities from the perspective of an investor who makes his money building, … Continue reading
Urgent: You have only 24 hours to sign up for a free DDR4 Webinar including just-released info from the JEDEC committee
I just heard from the Cadence memory interface guru himself, Marc Greenberg, about a DDR4 Webinar he’s giving tomorrow (Thursday) during the EETimes Virtual SoC event. Here’s what Marc wrote: “I am presenting a Webinar on DDR4 tomorrow (Thursday) at … Continue reading
You owe it to yourself to read Atrenta’s new SoC Realization White Paper. At 19 pages, you’ll need about half an hour to get through it, but if you and your company are at all involved in SoC development, then … Continue reading