Tag Archives: IBM

3D Thursday: Will water cooling for 3D IC assemblies ever be practical?

Posted on July 25, 2012 by sleibson2

Last week, Brian Bailey published an interview with Professor Madhavan Swaminathan who is the Director of the Interconnect and Packaging Center (IPC) at Georgia Tech in Atlanta. The topic of the interview was cooling of 3D IC devices. It’s no … Continue reading →

Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , , | Leave a comment

Can 1000 processors dance on the head of a pin? MIT’s Professor Srini Devadas hopes so

Posted on July 24, 2012 by sleibson2

Veteran EDA industry watcher Peggy Aycinena visited MIT recently and spoke with Professor Srini Devadas about a manycore processor project called “Angstrom.” The purpose of the project is to develop massively parallel hardware—as in 1024 processors—to explore better ways of … Continue reading →

Posted in Apps, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , , , , | Leave a comment

Hear IBM’s Dr. Gary Patton on the future of silicon scaling…and beyond. (Audio from The Common Technology Platform Forum keynote)

Posted on June 30, 2012 by sleibson2

Earlier this year, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center, spoke about the future of semiconductor scaling and beyond. It was a terrific keynote speech at the Common Platform Technology Forum and was similar to … Continue reading →

Posted in 10nm, 14nm, 20nm, 3D, EDA360, IBM, Silicon Realization | Tagged , , | Leave a comment

3D Thursday: ARM, HP, and SK hynix join Hybrid Memory Cube Consortium (HMCC)

Posted on June 28, 2012 by sleibson2

Add ARM, HP, and SK hynix to the growing list of companies in the Hybrid Memory Cube Consortium (HMCC). The three new members join the original founding companies, Micron and Samsung, along with Altera, IBM, Microsoft, Open-Silicon, and Xilinx plus … Continue reading →

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3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—“Learn to work together”

Posted on June 13, 2012 by sleibson2

Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about … Continue reading →

Posted in 2.5D, 3D, DAC, EDA360, Low Power, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , , , , | 5 Comments

3D Thursday: My breakfast with IBM’s Gary Patton leads to a discussion of 20nm and 14nm IC design

Posted on June 7, 2012 by sleibson2

Yesterday I moderated a panel on 2(x)nm success at DAC and one of the panelists was Dr. Gary Patton, VP of IBM’s Semiconductor Research and Development Center in East Fishkill, NY. I’ve heard Dr. Patton speak before and he knows … Continue reading →

Posted in 14nm, 20nm, 28nm, Double Patterning, EDA360, EUV, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , , | Leave a comment

Beyond breakfast: An ethical bribe for attending “The Path to Yielding at 2(x)nm and Beyond” at DAC

Posted on May 15, 2012 by sleibson2

Yesterday, I wrote about a terrific discussion panel about the challenges of 20nm design at DAC. I am moderating the panel and there will be speakers from the Common Platform partners including IBM, Samsung, GLOBALFOUNDRIES (just confirmed!), and Cadence. (See … Continue reading →

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Moore’s Law: Wanted, Dead or Alive

Posted on May 14, 2012 by sleibson2

Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held … Continue reading →

Posted in 20nm, 28nm, 32nm, 40nm, 65nm, EDA360, IBM, Low Power, Memory, Multicore, Packaging, TSV | Tagged , , , , , , , | 2 Comments

At DAC, take the path to successful 20nm design. The same path leads to breakfast. Wednesday, June 6

Posted on May 8, 2012 by sleibson2

If you’ve been following along—or even if you haven’t—Cadence held three 20nm Webinars last week. Perhaps you have to see it in person before you believe it. Fair enough. Here’s your chance to hear first-hand how you can develop high-yielding … Continue reading →

Posted in 20nm, EDA360, IBM, Samsung, Silicon Realization, SoC, SoC Realization | Tagged , , , | Leave a comment

3D Thursday: 3D IC success stories—a DAC panel. June 7

Posted on May 2, 2012 by sleibson2

What better way to understand the realities of 3D IC assembly than to listen to the pioneers who have already taken the arrows so you won’t have to? That’s the topic of the upcoming DAC panel: “Is 3-D Ready for … Continue reading →

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Three free Webinars answer your questions on 20nm SoC design. What questions do you have?

Posted on April 25, 2012 by sleibson2

What can you reasonably expect to get from 20nm? What does it take to implement an ARM Cortex-A15 processor in 20nm? What might come between you and success at 20nm? How can you be more productive when creating 20nm designs? … Continue reading →

Posted in 20nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , | Leave a comment

What are the challenges of EUV lithography and the issues surrounding double patterning? CDNLive! presentation provides details.

Posted on April 3, 2012 by sleibson2

Richard Goering has just published an excellent blog post on double patterning for 20nm and 14nm process geometries in his blog Industry Insights. The post is based on a paper presented by IBM Distinguished Engineer Lars Liebman at the recent … Continue reading →

Posted in 14nm, 20nm, Double Patterning, EDA360, EUV, Silicon Realization | Tagged , , , , , , | Leave a comment

3D Thursday: Micron to present Hybrid Memory Cube status at EDPS in Monterey, April 6—there’s a lot of news

Posted on March 29, 2012 by sleibson2

I’ve already written many blog entries about the Micron Hybrid Memory Cube (HMC), a 3D stacked memory device that can deliver a theoretical DRAM bandwidth of 128Gbytes/sec to a host system using a 4-die stack of DRAM (NOT SDRAM) on … Continue reading →

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Common Platform: Why do these companies (IBM, Samsung, GLOBALFOUNDRIES) collaborate?

Posted on March 19, 2012 by sleibson2

Ana Hunter, Foundry Services VP at Samsung Semiconductor, had the honor of kicking off the Global Technology Forum in Silicon Valley. She decided to devote her short intro speech to answering the basic question about the Common Platform—a partnership among … Continue reading →

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Want to know what’s going to happen at 20nm, 14nm, and beyond? A few answers from Frank Leu of Cadence

Posted on March 19, 2012 by sleibson2

Last week at the Global Technology Forum held at the Santa Clara Convention Center in Silicon Valley, Cadence VP of R&D Frank Leu discussed the things we’ve learned about 20nm IC manufacturing, what we are learning about 14nm, and where … Continue reading →

Posted in 14nm, 20nm, 28nm, EDA360, Globalfoundries, Samsung, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , | 2 Comments

3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet

Posted on March 7, 2012 by sleibson2

This week at the Optical Fibre Communication Conference and Exposition (OFC) in Los Angeles, Altera demonstrated a specially modified Stratix IV FPGA that handled bidirectional 100Gbps Ethernet (100GbE) traffic over a pair of IC-package-mounted Avago MicroPOD multi-lane optical transceivers. The … Continue reading →

Posted in 3D, EDA360, Packaging, Silicon Realization, SoC, SoC Realization | Tagged , , , , , | 2 Comments

By the numbers: 20nm (and 40nm, 32nm, 28nm, and 14nm) design to be discussed in technical detail at next week’s CDNLive! conference in Silicon Valley

Posted on March 5, 2012 by sleibson2

There’s still time to register for CDNLive!, which is being held on March 13 and 14 at the Doubletree Hotel in San Jose, California so let me give you a few numbers to whet your appetite: 40nm, 32nm, 28nm, 20nm, … Continue reading →

Posted in 14nm, 20nm, 28nm, 32nm, 40nm, CDNLive!, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , , , , | Leave a comment

Friday Video: Common Platform Technology Forum reveals program agenda, rolls into Silicon Valley on March 14

Posted on March 2, 2012 by sleibson2

The Common Platform partners are IBM, Samsung, and GLOBALFOUNDRIES and their annual Technology Forum  rolls into Silicon Valley on March 14, so you have a couple of weeks to sign up. This short video from ChipEstimate.com gives you a good … Continue reading →

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3D Thursday: Three on 3D—papers from ISSCC

Posted on March 1, 2012 by sleibson2

San Francisco Tech writer Rik Myslewski just published a long article on the UK’s “The Register” Web site covering three 3D papers given at last week’s ISSCC. The papers were presented by IBM (“3D system prototype of an eDRAM cache … Continue reading →

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GSA Silicon Summit to highlight cutting-edge IC technologies: 3D IC assembly, FinFETs, and SOI. April 26, Silicon Valley

Posted on February 7, 2012 by sleibson2

The Global Semiconductor Alliance (GSA) is sponsoring a half-day event that will drill down into three of the leading-edge IC manufacturing technologies of the coming decade: 3D (and 2.5D) IC assembly, FinFETs (or Tri-gate FETs), and silicon-on-insulator (SOI) substrates. The … Continue reading →

Posted in 2.5D, 20nm, 28nm, 32nm, 3D, EDA360, FDSOI, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , | 1 Comment

IBM to manufacture 32nm SOI chips with eDRAM in new GLOBALFOUNDRIES Fab 8 (Malta, NY)

Posted on January 10, 2012 by sleibson2

IBM is the first announced customer for GLOBALFOUNDRIES’ Fab 8 in Malta, NY. The companies plan to manufacture IBM’s 32nm SOI devices at the site using an SOI process technology. The new plant has already been facilitized with more than … Continue reading →

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3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it?

Posted on December 28, 2011 by sleibson2

For the last 3D Thursday blog post of 2011in the EDA360 Insider, I thought I’d take a flight of fancy and try to put as many of this year’s 3D IC concepts as possible together to see what we might … Continue reading →

Posted in 2.5D, 3D, EDA360, Memory, SoC, SoC Realization, System Realization | Tagged , , , , , , | Leave a comment

3D Thursday: Hybrid Memory Cube—Does anyone know what’s happening with IBM and Micron?

Posted on December 1, 2011 by sleibson2

This week, IBM and Micron apparently made a joint announcement (or perhaps just IBM made an announcement) regarding the manufacture of Micron’s Hybrid Memory Cube. There are varying reports and I cannot find the original statements on either company’s Web … Continue reading →

Posted in EDA360, Low Power, Memory, SoC, SoC Realization, System Realization, TSV | Tagged , , , | Leave a comment

3D Thursday (early): Steve’s Improbable History of 3D ICs? Six decades of 3D electronic packaging

Posted on November 9, 2011 by sleibson2

Last week at the 9th International SoC Conference in Newport Beach, I moderated a 3D IC panel that did a great job of exploring today’s state of the art for 3D IC development. I will be blogging the presentations made … Continue reading →

Posted in 28nm, 3D, EDA360, Low Power, Memory, TSV | Tagged , , , , , , , , , , , | 1 Comment

3D Thursday: Feedback on last week’s blog post about 3M/IBM agreement to work on heat-conductive 3D assembly adhesives

Posted on September 15, 2011 by sleibson2

Last Thursday, I wrote a blog entry on the agreement between IBM and 3M to develop advanced adhesives to aid in 3D die-stack assembly and heat removal. (See “3D Thursday: Can IBM and 3M really build a 3D, 100-chip stairway … Continue reading →

Posted in 3D, EDA360, Packaging, Silicon Realization | Tagged , | Leave a comment