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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud
- 3D IC
- ARM architecture
- ARM Cortex-A15
- Dave Jones
- Double Patterning
- Field-programmable gate array
- Flash memory
- Freescale Semiconductor
- Jim Hogan
- Low Power
- Mixed Signal
- Multi-core processor
- Printed circuit board
- Texas Instruments
- Wide I/O
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- Asynchronous FIFO design disaster forces silicon respin. A cautionary SoC design tale from the trenches.
- What about the Denali Party? The big question for DAC 2011 is now answered.
- Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP
- Vizio (!) introduces line of high-end Windows PCs and notebooks. Didn’t they didn’t read that “post-PC” memo?
- New Mixed-Signal Methodology Guide provides design, verification and implementation methodologies for advanced mixed-signal designs
- Friday Video: SpaceShipTwo is a perfect example of a way to “Think Different” for System and SoC Realization teams
- Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?
Download the EDA360 Vision Paper here:
Category Archives: 3D
There’s a strange little high-rise hotel called the Biltmore in the center of Silicon Valley at the intersection of the Montague Expressway and Highway 101. It’s going to be the site of this year’s “Roadmaps for Multi Die Integration” conference … Continue reading
3D Thursday: Produce cost-effective 2.5D and 3D devices. Attend the Known Good Die conference, November 15
Robert Patti, Chief Technical Officer and VP of Design Engineering at Tezzaron Semiconductor is the just-announced speaker at the Known Good Die conference being held on November 15 in Santa Clara, CA. His topic: Using Repair & Redundancy with KGD … Continue reading
3D Thursday: Intel Penwell SoC for mobile phones employs POP (package-on-package) LPDDR2 SDRAM to reduce power
Wednesday at the Hot Chips 24 conference, Rumi Zahir of Intel discussed the company’s Penwell SoC designed for cell phone handsets. The SoC is employed in the Medfield cellular handset design and it’s based on the Intel Atom x86 processor … Continue reading
This week is being consumed by the Flash Memory Summit. 3D Thursday will return next week. Thanks for standing by.
3D Thursday: Save the date. 3D Architectures for Semiconductor Integration and Packaging Conference on December 12-14
The 9th International 3-D Architectures for Semiconductor Integration and Packaging Conference and Exhibition will be held December 12 -14, 2012 at the Sofitel in Redwood City, CA. It’s run by RTI International. More info here.
Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading
Last week, Brian Bailey published an interview with Professor Madhavan Swaminathan who is the Director of the Interconnect and Packaging Center (IPC) at Georgia Tech in Atlanta. The topic of the interview was cooling of 3D IC devices. It’s no … Continue reading
If you’re looking for simplified explanations of technical topics, few people write them as well as Clive “Max” Maxfield. His simplified 3-page explanation of 3D IC assembly is here. (Note: Registration needed to go past page 1, unfortunately.)
A new “Experts at the Table” conversation on the Semiconductor Manufacturing and Design Community (SMD) site about IP Subsystems among Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; … Continue reading
Yesterday, Micron announced volume production of a new memory device containing one 1Gbit PCM (phase-change memory) die and one 512Mbit LPDDR2 SDRAM die. The two die reside in the device package as stacked die, with wire-bonded interconnect. This is a … Continue reading
3D Thursday: Want some real-world insight into 2.5D and 3D IC design and assembly? Read on to get the word from Tezzaron Semiconductor
Ann Steffora-Mutschler just published an interview with Robert Patti, chief technology officer at Tezzaron Semiconductor, that gives some terrific technical detail about 2.5D and 3D IC design and assembly. Patti provides some rare insight into today’s (as in right now) … Continue reading
3D Thursday: What the Cadence purchase of signal- and power-integrity EDA toolmaker Sigrity means for 2.5D and 3D IC assembly
Richard Goering has just published an in-depth analysis in his Industry Insights blog that explains what the Cadence purchase of signal- and power-integrity EDA toolmaker Sigrity means for pcb and IC package designers. Goering quotes Brad Griffin, product marketing director … Continue reading
Today I was reading this week’s issue of Time Magazine while eating lunch in my secret fish-and-chips restaurant at an undisclosed location in Milpitas, California when I chanced upon a fascinating article about RIM, maker of the BlackBerry. The article’s … Continue reading
Hear IBM’s Dr. Gary Patton on the future of silicon scaling…and beyond. (Audio from The Common Technology Platform Forum keynote)
Earlier this year, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center, spoke about the future of semiconductor scaling and beyond. It was a terrific keynote speech at the Common Platform Technology Forum and was similar to … Continue reading
Add ARM, HP, and SK hynix to the growing list of companies in the Hybrid Memory Cube Consortium (HMCC). The three new members join the original founding companies, Micron and Samsung, along with Altera, IBM, Microsoft, Open-Silicon, and Xilinx plus … Continue reading
Quoting a corporate press release, the Web site http://www.dpreview.com reports that Sony Corp intends to invest approximately 80 billion Yen through the end of March, 2014 to expand its capacity to manufacture “stacked silicon sensors,” which are 3D IC assemblies … Continue reading
Last week on the EDA Café Web site, EDA Editor and Industry Observer Gabe Moretti discussed my DAC blog post on Wally Rhines’ discussion of software’s role in the rising cost of SoC development. (See “Some chip-design reality from Mentor’s … Continue reading
Vizio (!) introduces line of high-end Windows PCs and notebooks. Didn’t they didn’t read that “post-PC” memo?
Today, “America’s #1 LCD HDTV” vendor Vizio launched a line of sleek notebook, ultrabook, and all-in-one desktop PCs. Howzat? Isn’t Vizio familiar with the term “post-PC era”? What have they been smoking down there in Irvine? I think Vizio is … Continue reading
I conducted this video interview with Herb Reiter, “Mr. 3D IC” and president of eda2asic, the day after he spoke at a MEPTEC lunch in Silicon Valley—see “3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—‘Learn … Continue reading
Briefly noted: SemiWiki’s Paul McLellan has just published a short analysis of the 3D announcements made last week at DAC by TSMC and Cadence.
Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about … Continue reading
Richard Goering just published a detailed blog post about the TSMC 2.5D/3D IC test vehicle, which TSMC is calling CoWoS (Chip on Wafer on Substrate) in his Industry Insights blog. This approach to 3D IC assembly bonds active silicon die … Continue reading
Friday Video + 3D Thursday: Xilinx Virtex-7 H580T uses 3D assembly to merge 28Gbps xceivers, FPGA fabric
The first 3D part in the Xilinx Virtex-7 FPGA family—the 2000T—permitted the construction of a huge FPGA while sidestepping the yield issues of large 28nm die. Now, Xilinx has used 3D IC assembly to meld two FPGA logic slices and … Continue reading
3D Thursday: Electronics Component and Technologies Conference in San Diego features several 3D learning opportunities. May 29-June 1.
The Electronics Component and Technologies Conference being held in San Diego on May 29-June 1 will provide you with several significant opportunities to come up to speed on 3D IC assembly and related topics including: Session 1 on 3D Interconnect … Continue reading
What better way to understand the realities of 3D IC assembly than to listen to the pioneers who have already taken the arrows so you won’t have to? That’s the topic of the upcoming DAC panel: “Is 3-D Ready for … Continue reading