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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- Asynchronous FIFO design disaster forces silicon respin. A cautionary SoC design tale from the trenches.
- What about the Denali Party? The big question for DAC 2011 is now answered.
- Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP
- Vizio (!) introduces line of high-end Windows PCs and notebooks. Didn’t they didn’t read that “post-PC” memo?
- New Mixed-Signal Methodology Guide provides design, verification and implementation methodologies for advanced mixed-signal designs
- Friday Video: SpaceShipTwo is a perfect example of a way to “Think Different” for System and SoC Realization teams
- Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?
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Tag Archives: Medfield
3D Thursday: Intel Penwell SoC for mobile phones employs POP (package-on-package) LPDDR2 SDRAM to reduce power
Wednesday at the Hot Chips 24 conference, Rumi Zahir of Intel discussed the company’s Penwell SoC designed for cell phone handsets. The SoC is employed in the Medfield cellular handset design and it’s based on the Intel Atom x86 processor … Continue reading
Posted in 3D, EDA360, Packaging, Silicon Realization, SoC, SoC Realization, System Realization
Tagged eMMC, Intel, Intel Atom, LPDDR2, Medfield, mobile phone, SDRAM, SoC
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