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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Friday Video: Ready for a little mobile phone teardown archaeology? Dave Jones compares state of the art in 1994 (Motorola) with an evolved 2000 (Nokia)
- 20nm design: What have we learned so far?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
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Tag Archives: Analog
Workshop on Analog and Mixed-Signal Design Automation: November 8 in Silicon Valley
A 1-day workshop on Analog and Mixed-Signal Design Automation will be held on November 8 in conjunction with ICCAD in Silicon Valley. It’s no secret that advanced-node process scaling makes all IC design more complex and more challenging—even more so … Continue reading
FREE Webinar on analog verification. Wednesday, May 9 at 9:00 am PST
Analog blocks are usually verified at the block level many things still go wrong with connectivity and control of the analog circuit at the SoC level. It’s not enough to integrate these analog blocks into digital simulations; you need to … Continue reading
Posted in Analog, EDA360, Mixed Signal, Silicon Realization, Verification
Tagged AMS, Analog, Mixed Signal, SV-AMS, SystemVerilog, verification
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3D Thursday: 3D ICs and analog chips. Where’s the match? Is there a match?
Dr. Venu Menon, VP of Analog Technology Development at TI, gave a deeply informative lunchtime keynote speech at this week’s ISQED Symposium. Most of Menon’s presentation discussed analog process technology: what’s important to analog chip design and manufacturing, what’s changed … Continue reading
Posted in 3D, EDA360, Silicon Realization
Tagged Analog, IC packaging, ISQED Symposium, TSV
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Free Webinar on December 8: Mixed-signal and low-power analysis and verification techniques
As the size and complexity of mixed-signal designs have grown, so has the verification task. Designers face the challenging task of verifying complex power, performance, and functionality specifications as well as validating analog and digital interactions over a broad range … Continue reading
Posted in AMS, EDA360, Silicon Realization, SoC, Verification
Tagged Analog, ASIC, Low Power, Mixed Signal
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Who else wants to overcome power-related IR-drop and electromigration challenges in mixed-signal ASIC designs?
How many times have you discovered unanticipated IR drop or electromigration problems in the power grids of your complex analog or mixed-signal ASIC? How easy was it to fix these problems? Virtually all modern IC and SoC designs include mixed … Continue reading
Posted in EDA360, Silicon Realization
Tagged Analog, ASIC, electromigration, IR drop, Mixed Signal
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Learn how an analog design flow can boost your IC design productivity…FREE (Breakfast and Lunch too!)
You’ve got just a few days only before the new series of free technical seminars on analog design flows for analog, mixed-signal, and custom designs can boost your team’s design productivity. The key to boosting design productivity is reducing design … Continue reading
Posted in Design Abstraction, Design Convergence, Design Intent, EDA360, Silicon Realization
Tagged Analog, Mixed Signal
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Triad Semi brews potent analog/digital/ARM-processor mixes with its via-programmable arrays
Real System Realization involves the delicate balancing of many factors including performance, power, and cost. Each of these factors consists of many subcomponents. For example, most performance requirements have mixed-signal aspects and include both digital and analog components. Triad Semiconductor … Continue reading
Posted in EDA360, Silicon Realization, SoC Realization, System Realization
Tagged Analog, ASIC, gate array, Triad, Triad Semiconductor
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Intel says Moore’s Law alive and well and living at 32nm
One of the really interesting presentations at least week’s 8th International SoC Conference in Irvine was from Dr Jeff Parkhurst, Research Programs Manager at Intel, who spoke on the topic of “Delivering Cost-effective SoC-Based Platform Solutions.” I found the presentation … Continue reading
Posted in EDA360, IP, Silicon Realization, SoC Realization
Tagged AMS, Analog, Mixed/Signal. Intel
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Free EDA Seminar Day: Analog, Mixed Signal, RF Silicon Realization, Simulation, Verification, Power. Bracknell, UK. November 17, 2010.
Ready to propel your analog, mixed-signal, and RF Silicon Realization efforts into the future? If you can manage to be in Bracknell, UK (just west of London on the M4) this November 17, you can brush up for a full … Continue reading
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