Tag Archives: EDA

Jim Hogan wants to give you the secrets of raising funds for an EDA startup. Free!

On October 17, Jim Hogan’s second “conversation” in his Emerging Companies Series will deal with a key topic for EDA entrepreneurs: “How to Raise Money and How Not to Spend It.” Hogan’s guests include Amit Gupta, President and CEO of … Continue reading

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DAC 2012: Get answers to all of your EDA questions at 78 Cadence demo suite slots

Next week (Monday, Tuesday, and Wednesday) you can get all of your EDA questions answered at the Cadence DAC demo suites. There are 78 demos over the three days covering the following EDA topics: Mixed-signal and low-power design RTL-to-GDSII design … Continue reading

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Gary Smith’s Sunday Pre-DAC talk to focus on Multi-platform-based SoC Design Methodology

For years, EDA Analyst Gary Smith has given a pre-DAC talk on the major trends in EDA and in the design of SoCs and ICs. This year is no exception. Smith has reserved Salon 6 at the San Francisco Marriott … Continue reading

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Free live discussion on how you can develop the next great EDA company with host and perennial EDA VC Jim Hogan

EDAC is sponsoring a new live discussion series on emerging companies in the EDA industry. The first of these events takes place on May 31 in San Jose at the Silicon Valley Bank on Tasman near Great America Parkway. The … Continue reading

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3D preview from EDPS: Qualcomm’s Director of Engineering Riko Radojcic talks 3D and 3D EDA

Last week’s Electronic Design Process Symposium (EDPS) opened a rich new vein of 3D IC material and you’ll see a lot nuggets from me on that topic in the next few days. Meanwhile, Richard Goering has already published a post … Continue reading

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Tales from the EDA CEOs: The EDAC panel talks about IP and SoC integration, power, and other topics

Richard Goering has written up last week’s EDA CEO panel, sponsored by EDAC (the EDA Consortium). The panel took place at the Silicon Valley Bank’s headquarters in Santa Clara, California and featured CEOs from four EDA companies—Cadence (Lip-Bu Tan), Gradient … Continue reading

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Less than two weeks left for early-bird EDPS registration. Don’t miss 3D Friday, the other EDA speakers, or your chance to network for that matter

EDPS (The Electronic Design Process Symposium) provides a dynamic venue for the exchange of ideas among the top thinkers, movers, and shakers in EDA, who focus on how chips and systems are designed in the electronics industry. Attendees of this … Continue reading

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Hardware/Software Codesign: Pink elephants on parade?

As part of this week’s DVCon event being held in Silicon Valley, the EDAC Emerging Companies Committee sponsored a really intense and well-attended evening panel on hardware/software codesign. The effervescent Paul McLellan moderated the panel. (If you’ve not read his book, … Continue reading

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System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang

Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading

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IEEE Computer Society Lecture—Creating System-On-Chips: Mixing HW & SW Successfully

As soon as we started to incorporate processors on ASICs, thus instantly creating SoCs, hardware/software integration issues became fully intertwined with chip design. Today, we routinely put a dozen or more firmware-driven processing elements on our SoCs so the issues … Continue reading

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EDA VC Jim Hogan to connect the dots between user experience and SoC Realization at EDPS in April

It’s pretty hard to go from high-level customer expectations for an end product to the definition of an SoC. If it were easy, everyone would be able to do it. You have a unique chance to hear EDA venture capitalist … Continue reading

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Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0

Chocolate and peanut butter go together. So do SystemC and transaction-level modeling. Just not officially. Until now. Earlier this month, the IEEE Standards Board approved a revision to the IEEE 1666 SystemC standard to bring the widely used OSCI (Open … Continue reading

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Another blog entry about getting all of the performance you purchased from your EDA tools

Back in September, I wrote a blog entry titled “10 ways to get your EDA tools to run faster, smoother, and longer” based on an interview with Peter Vincent, who is with the Cadence EDA Infrastructure Acceleration Services team. Richard … Continue reading

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EDA Consultant? Here’s your chance to strut your stuff in front of a prime audience

If you are an EDA consultant looking for clients, then marketing takes a chunk of your time. How about some prime face time in front of hundreds of prospects? If you are an expert in working with Cadence EDA tools … Continue reading

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10 ways to get your EDA tools to run faster, smoother, and longer

The IT troubleshooter drops his pack into a chair across the table from me and sits down. “We take care of…problems” he says. The problems he’s referring to are sluggish EDA tools. Perhaps you’ve encountered a few. Perhaps you suspected … Continue reading

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A bit of SoC Realization wisdom from Paul McLellan

Industry analyst, EDA investor, and author of “EDA Graffiti”—those are just a few of Paul McLellan’s qualifications. He just published a pithy comment on SoC Realization and its realities over on the SemiWiki site. I commend it to your attention.

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