EDPS (The Electronic Design Process Symposium) provides a dynamic venue for the exchange of ideas among the top thinkers, movers, and shakers in EDA, who focus on how chips and systems are designed in the electronics industry. Attendees of this elite workshop have met each year in Monterey, California since 1993. EDPS attracts some of the most far-seeing people and other luminaries in the electronics industry as speakers. It’s a forum for discussing EDA’s state-of-the-art and state-to-be with an eye towards improving electronics design processes and EDA/CAD methodologies, rather focusing on individual tools themselves. This year, EDPS takes place on Thursday, April 5 and Friday, April 6.
Also this year, EDPS features 3D Friday (April 6), a day wholly devoted to discussions of 3D IC assembly and manufacture. Few changes on the industry’s event horizon promise to rework electronics the way 3D does. Such revolutions have occurred in the past. Transistors, printed circuit boards, integrated circuits, microprocessors, surface-mount technology, FPGAs, ASICs, and SoCs are some of the big changes that have occurred in the past. 3D IC assembly promises to be one of those changes and will be extensively discussed at EDPS.
The keynoter for 3D Friday is Riko Radojcic, Director of Design for Silicon Initiatives at Qualcomm. His keynote subject is “Roadmap for Design and EDA Infrastructure for 3D Products.” Qualcomm is neck-deep in semiconductor design for mobile communications, which means high manufacturing volumes, voracious cost-management requirements, and steep competition among big and emerging players. All of these needs inform and drive Radojcic’s perspective, so his keynote promises to be extremely interesting.
Early-bird registration ends on March 18. After that, registration prices go up and you really don’t want to have that happen. So go and register now, just click here.
Not convinced yet? That’s OK. Take a look at the entire program. Click here.
