Tag Archives: 3D

3D Thursday: Save the date. 3D Architectures for Semiconductor Integration and Packaging Conference on December 12-14

The 9th International 3-D Architectures for Semiconductor Integration and Packaging Conference and Exhibition will be held December 12 -14, 2012 at the Sofitel in Redwood City, CA. It’s run by RTI International. More info here. Advertisements

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3D Thursday: Will water cooling for 3D IC assemblies ever be practical?

Last week, Brian Bailey published an interview with Professor Madhavan Swaminathan who is the Director of the Interconnect and Packaging Center (IPC) at Georgia Tech in Atlanta. The topic of the interview was cooling of 3D IC devices. It’s no … Continue reading

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3D Thursday: Magnificent Max explains 3D IC in simple terms

If you’re looking for simplified explanations of technical topics, few people write them as well as Clive “Max” Maxfield. His simplified 3-page explanation of 3D IC assembly is here. (Note: Registration needed to go past page 1, unfortunately.)

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3D Thursday: Want some real-world insight into 2.5D and 3D IC design and assembly? Read on to get the word from Tezzaron Semiconductor

Ann Steffora-Mutschler just published an interview with Robert Patti, chief technology officer at Tezzaron Semiconductor, that gives some terrific technical detail about 2.5D and 3D IC design and assembly. Patti provides some rare insight into today’s (as in right now) … Continue reading

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3D Thursday (Late): Sony to invest 80 billion Yen in stacked CMOS sensor manufacturing expansion

Quoting a corporate press release, the Web site http://www.dpreview.com reports that Sony Corp intends to invest approximately 80 billion Yen through the end of March, 2014 to expand its capacity to manufacture “stacked silicon sensors,” which are 3D IC assemblies … Continue reading

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Friday Video: Mr. 3D IC, Herb Reiter, speaks about his start with 3D, where it is, where it’s going

I conducted this video interview with Herb Reiter, “Mr. 3D IC” and president of eda2asic, the day after he spoke at a MEPTEC lunch in Silicon Valley—see “3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—‘Learn … Continue reading

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3D Thursday: SemiWiki’s Paul McLellan on the TSMC/Cadence 3D collaboration

Briefly noted: SemiWiki’s Paul McLellan has just published a short analysis of the 3D announcements made last week at DAC by TSMC and Cadence.

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3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—“Learn to work together”

Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about … Continue reading

Posted in 2.5D, 3D, DAC, EDA360, Low Power, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , , , , | 5 Comments

3D Thursday: Want to see a closeup of the TSMC 3D IC test vehicle?

Richard Goering just published a detailed blog post about the TSMC 2.5D/3D IC test vehicle, which TSMC is calling CoWoS (Chip on Wafer on Substrate) in his Industry Insights blog. This approach to 3D IC assembly bonds active silicon die … Continue reading

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Friday Video + 3D Thursday: Xilinx Virtex-7 H580T uses 3D assembly to merge 28Gbps xceivers, FPGA fabric

The first 3D part in the Xilinx Virtex-7 FPGA family—the 2000T—permitted the construction of a huge FPGA while sidestepping the yield issues of large 28nm die. Now, Xilinx has used 3D IC assembly to meld two FPGA logic slices and … Continue reading

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Moore’s Law: Wanted, Dead or Alive

Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held … Continue reading

Posted in 20nm, 28nm, 32nm, 40nm, 65nm, EDA360, IBM, Low Power, Memory, Multicore, Packaging, TSV | Tagged , , , , , , , | 2 Comments

3D Thursday: Electronics Component and Technologies Conference in San Diego features several 3D learning opportunities. May 29-June 1.

The Electronics Component and Technologies Conference being held in San Diego on May 29-June 1 will provide you with several significant opportunities to come up to speed on 3D IC assembly and related topics including: Session 1 on 3D Interconnect … Continue reading

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3D Thursday: 3D IC success stories—a DAC panel. June 7

What better way to understand the realities of 3D IC assembly than to listen to the pioneers who have already taken the arrows so you won’t have to? That’s the topic of the upcoming DAC panel: “Is 3-D Ready for … Continue reading

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3D Thursday: Practical Approaches to 3-D IC—TSV/Silicon Interposer and Wide IO Implementation From People Who Have Been There, Done That

If you’re like me, you’ve heard more than enough theory about 3D IC assembly and you’re ready to get on with the main event and design something. Want to hear about 3D IC technology that works? Now? Then you will … Continue reading

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3D Thursday: A funny thing happened to me on the EDPS 3D-IC panel

Last Friday, I moderated an all-star, hand-picked 3D-IC panel at the Electronic Design Process Symposium (EDPS) in Monterey, California. The panel included: Phil Marcoux, Managing Director, PPM Associates, experienced packaging expert Herb Reiter, President of eda2asic, Chair of the Global … Continue reading

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Want a peek at a possible Qualcomm 3D IC roadmap?

“3D IC test wafers will run this year and high-volume 3D IC manufacturing will start in 2013,” concluded Riko Radojcic at the end of his EDPS keynote on 3D ICs held in Monterey, California last Friday. Radojcic is Qualcomm’s Director … Continue reading

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3D Thursday: A quick look at glass interposers for 3D IC assembly

3D InCites just published a short piece on glass interposers for 3D ICs, as discussed at the 2012 IMAPS International Device Packaging conference, held March 5-8 in Scottsdale, AZ. If you’re interested in seeing a more technical presentation on the … Continue reading

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3D Thursday: TSMC talks more about Moore, More than Moore, and 3D ICs at CDNLive!

Rick Cassidy, president of TSMC North America, gave a keynote speech at CDNLive! Silicon Valley this week and discussed 3D IC assembly in the context of Moore’s Law. “I think we can actually beat Moore,” he said after discussing planar … Continue reading

Posted in 10nm, 14nm, 2.5D, 3D, CDNLive!, EDA360, Packaging, Silicon Realization, SoC, SoC Realization | Tagged , , , , | Leave a comment

EDPS 3D Friday (April 6) expands with new speakers including 3D IC assembly and packaging advocate Phil Marcoux

I’ve written previously about the all-3D IC design, assembly, and packaging program that will take place during the second day of the EDPS (Electronic Design Process Symposium) workshop in Monterey. This blog post is to let you know that additional … Continue reading

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Tales from the EDA CEOs: The EDAC panel talks about IP and SoC integration, power, and other topics

Richard Goering has written up last week’s EDA CEO panel, sponsored by EDAC (the EDA Consortium). The panel took place at the Silicon Valley Bank’s headquarters in Santa Clara, California and featured CEOs from four EDA companies—Cadence (Lip-Bu Tan), Gradient … Continue reading

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3D Thursday: Three on 3D—papers from ISSCC

San Francisco Tech writer Rik Myslewski just published a long article on the UK’s “The Register” Web site covering three 3D papers given at last week’s ISSCC. The papers were presented by IBM (“3D system prototype of an eDRAM cache … Continue reading

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3D Thursday (late): Qualcomm’s Riko Radojcic to keynote 3D Friday at EDPS in Monterey, April 6

EDPS—the world’s “best” conference devoted to discussing the processes needed for advanced electronic design—is dedicating its entire second day (Friday, April 6) to 3D IC topics. The just-announced keynote speaker is Riko Radojcic, Director of Design for Silicon Initiatives at … Continue reading

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3D Thursday: EDPS conference features 3D Friday

The Electronic Design Process Symposium soon to be held in Monterey, California, will devote all of Friday, April 6 to 3D IC issues. There will be three morning presentations and a 5-person panel in the afternoon. The EDPS Program Web … Continue reading

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3D Thursday: Is Wide I/O SDRAM free for the end user???

A recent email from Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, suggested that Wide I/O used in a 3D stack is free for the end user. In other words, there’s no incremental cost in the … Continue reading

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3D Thursday: Mark LaPedus writes overview of the 3D IC landscape

Briefly noted: Over at the Semiconductor Manufacturing & Design Community, Senior Editor Mark LaPedus has just published an article that’s a good review of the various challenges to 3D IC adoption including: Known good die Testability Design for test Standards … Continue reading

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