Tag Archives: TSMC

Where do semiconductor foundries come from?

Have you ever wondered how we got from a world solely occupied by semiconductor vendors with their own fabs to today’s hodgepodge of IDMs (independent device manufacturers, the new name for the old-style “semiconductor vendor”), fab-lite vendors, and fables vendors? … Continue reading

Advertisement

Posted in EDA360, Silicon Realization | Tagged , , | Leave a comment

Need to make an ARM Cortex-A9 processor core all it can be?

A new blog published today on the ARM Web site titled “How do you take an ARM POP up one more notch?” describes a very recent collaboration between ARM and Cadence to enhance the ARM POP IP, which helps any … Continue reading

Posted in 40nm, ARM, Cortex-A9, Silicon Realization, SoC, SoC Realization, TSMC | Tagged , , , , | Leave a comment

ARM, TSMC announce collaboration on FINfet-based ARM v8 processor core for sub-20nm SoC designs

Today, ARM and TSMC announced a multi-year deal to develop a 64-bit ARM v8 processor “beyond” the 20nm node using FINfets. The collaboration includes the ARMv8 architecture, ARM Artisan physical IP, and TSMC’s FinFET process technology. The target of this … Continue reading

Posted in 10nm, 14nm, 20nm, ARM, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , | Leave a comment

Want details on the TSMC 20nm process technology?

Daniel Nenni has just published a great, short overview of the specifications for the TSMC 20nm process technology on his SemiWiki site. Nenni’s report hits the important benefits of the advanced process technology right at the beginning: 30% faster 1.9x … Continue reading

Posted in 20nm, TSMC | Tagged , , , , | 1 Comment

3D Thursday: SemiWiki’s Paul McLellan on the TSMC/Cadence 3D collaboration

Briefly noted: SemiWiki’s Paul McLellan has just published a short analysis of the 3D announcements made last week at DAC by TSMC and Cadence.

Posted in 2.5D, 3D, System Realization | Tagged , , , | Leave a comment

3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—“Learn to work together”

Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about … Continue reading

Posted in 2.5D, 3D, DAC, EDA360, Low Power, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , , , , | 5 Comments

Are you preparing for 20nm design? This FREE On-Demand Webinar can help.

Last week ARM, TSMC, and Cadence held a Webinar on 20nm design covering three main points: Its adoption is inevitable. The design and manufacturing challenges are significant. The challenges are manageable given the right tools and methodologies, and solutions are … Continue reading

Posted in 20nm, EDA360, Silicon Realization | Tagged , , , , , | Leave a comment

3D Thursday: 3D IC success stories—a DAC panel. June 7

What better way to understand the realities of 3D IC assembly than to listen to the pioneers who have already taken the arrows so you won’t have to? That’s the topic of the upcoming DAC panel: “Is 3-D Ready for … Continue reading

Posted in 2.5D, 3D, EDA360, Silicon Realization | Tagged , , , , , , , | Leave a comment

3D Thursday: Practical Approaches to 3-D IC—TSV/Silicon Interposer and Wide IO Implementation From People Who Have Been There, Done That

If you’re like me, you’ve heard more than enough theory about 3D IC assembly and you’re ready to get on with the main event and design something. Want to hear about 3D IC technology that works? Now? Then you will … Continue reading

Posted in 2.5D, 3D, Packaging, Silicon Realization, TSMC | Tagged , , , , , | Leave a comment

Three free Webinars answer your questions on 20nm SoC design. What questions do you have?

What can you reasonably expect to get from 20nm? What does it take to implement an ARM Cortex-A15 processor in 20nm? What might come between you and success at 20nm? How can you be more productive when creating 20nm designs? … Continue reading

Posted in 20nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , | Leave a comment

TSMC simplifies life at 20nm, will offer a single 20nm process technology

TSMC’s Executive Vice President and Co-Chief Operating Officer Dr. Shang-yi Chiang said at yesterday’s TSMC Symposium that the company will offer one process at the 20nm node, as reported by Dylan McGrath of EETimes. This position differs from the two- … Continue reading

Posted in 20nm, EDA360, Silicon Realization | Tagged , , | Leave a comment

Looking at 20nm design? Three free Webinars can help.

With the 20nm click on the process technology dial staring us in the face, you might be wanting some informative, experience-based help. Three free Webinars taking place on May 1, 2, and 3 will give you some extra oomph in … Continue reading

Posted in 20nm, EDA360, Silicon Realization, TSMC | Tagged , , , | Leave a comment

You have six weeks to wait for the Semico IP Summit. What will you do until then?

Use of IP in the design of SoCs has long been a fact. The very name “SoC” says that you’re using microprocessor IP at the very least. With that comes memory IP, memory controller IP, interface IP, analog IP, etc. … Continue reading

Posted in EDA360, IP, SoC Realization | Tagged , , , , , , | Leave a comment

3D Thursday: TSMC talks more about Moore, More than Moore, and 3D ICs at CDNLive!

Rick Cassidy, president of TSMC North America, gave a keynote speech at CDNLive! Silicon Valley this week and discussed 3D IC assembly in the context of Moore’s Law. “I think we can actually beat Moore,” he said after discussing planar … Continue reading

Posted in 10nm, 14nm, 2.5D, 3D, CDNLive!, EDA360, Packaging, Silicon Realization, SoC, SoC Realization | Tagged , , , , | Leave a comment

3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work

I recently covered the groundbreaking WIOMING 3D chip design done by CEA-Imec in conjunction with ST-Ericsson. (See “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. … Continue reading

Posted in 2.5D, 3D, EDA360, imec, SoC, SoC Realization | Tagged , , , , , , , , , , , , , , , | Leave a comment

3D Thursday: TSMC’s 3D plans and the word on 3D from Xilinx, Nvidia, IMEC, and STATS ChipPAC

For another take on last month’s RTI 3D conference held in Burlingame, CA, see Dr. Phil Garrou’s blog on the ElectroIQ site. Click here. For previous EDA360 Insider coverage of this event, see “3D Week: Wide I/O SDRAM, Network on … Continue reading

Posted in 3D, EDA360, Silicon Realization, SoC Realization, System Realization, TSMC | Tagged , , , , | Leave a comment

3D Thursday: TSMC honors Cadence 3D design tools with an EDA Partner Award

This week, Cadence announced that it had received a TSMC EDA Partner Award for its 3D-IC EDA tool technology, which TSMC used to implement an interposer test vehicle. You can read more here.

Posted in 3D, EDA360, Silicon Realization | Tagged | Leave a comment

What will EDA and chip design look like in the year 2020? Prognostications from the ICCAD panel

Last night, half a dozen ICCAD panelists attacked the topic “2020 Vision: What the recent history of EDA will look like in nine years.” That’s such a convoluted and hard-to-parse title that the panelists chose to discuss the state of … Continue reading

Posted in 20nm, 28nm, 3D, DAC, Design Abstraction, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , | 4 Comments

3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)

Tuesday, Xilinx announced that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, … Continue reading

Posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , | Leave a comment

Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)

Xilinx announced today that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, … Continue reading

Posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, TSV | Tagged , , , , , | Leave a comment

Want to know the secrets of implementing an ARM Cortex-A15 in an advanced process node? Read on!

ARM and Cadence have just announced the tape out of the industry’s first 20nm design based on the ARM Cortex-A15 MPCore processor. The test chip targets TSMC’s 20nm process and it was jointly developed by engineers from ARM, TSMC, and … Continue reading

Posted in ARM, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, TSMC | Tagged , , , , | Leave a comment

3D Thursday: EETimes backs away from an apples and oranges comparison. Makes fruit salad

Earlier in July, Dylan McGrath at EETimes published an article about a report that pitted TSMC and Intel in a race to 3D. Unfortunately, there’s not really a race. TSMC’s efforts are towards 3D chip assembly. That’s the kind of … Continue reading

Posted in 3D, EDA360, Silicon Realization, SoC Realization, System Realization | Tagged , | Leave a comment

3D Thursday: IMEC prototypes 3D chip stack, finds some thermal surprises

Imec and several of its 3D integration partners (Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Fujitsu, Sony, Amkor, and Qualcomm) have fabricated a 3-chip 3D IC stack demonstration prototype with the intent of proving several assembly methods plus electrical characteristics and … Continue reading

Posted in 3D, Silicon Realization, SoC Realization, System Realization, TSMC, TSV | Tagged , , , , , , , , , , | 1 Comment

Xilinx 28nm low-power SoC design class, part 3: Optimizing the transistor mix

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading

Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization | Tagged , , , | Leave a comment

Xilinx 28nm low-power SoC design class, part 2: Process Technology

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading

Posted in EDA360, Silicon Realization, SoC Realization, System Realization | Tagged , , , | Leave a comment