Xilinx 28nm low-power SoC design class, part 2: Process Technology

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This White Paper is an authoritative guide to the many ways you can cut static and dynamic power in nearly any chip design that will be manufactured at advanced process nodes like 28nm or 20nm. This White Paper is so incredibly comprehensive that I simply cannot summarize it in one blog entry, so I have sliced it into six relevant pieces and am discussing the most significant topics over several blog entries, one each day this week. Be sure to come back each day for the next installment in the series.

Today’s discussion is about selecting a low-power IC process technology. It’s not as intuitive as you might think.

Xilinx has chosen TSMC’s 28 HPL process to make all of the Series 7 FPGA family members (Virtex-7, Kintex-7, and Artex-7) over TSMC’s 28 HP and 28 P process technologies but instead of letting us know this fact and leaving it there, the Xilinx White Paper goes into great detail about the decision. It’s an instructive line of thought, so I will summarize it here. Be sure to get and read the White Paper for further details.

First, you should know that Xilinx considered all three of the TSMC 28nm process technologies for the 7-series FPGA families but the company quickly locked on the two high-K metal-gate (HKMG) processes (HP and HPL) as being the “best” for FPGA design. Because Xilinx wanted to use just one process technology to cover all of the planned Series-7 FPGA families from high-performance to low-power, HKMG promised the best mix of performance and leakage for the company’s unified approach to designing all of the Series-7 FGPA families. TSMC’s 28 LP process uses PolySiON (polysilicon/silicon oxy-nitride) gate insulation and is best suited for designs that require less performance than FPGAs according to the Xilinx White Paper. The PolySiON 28 LP process produces transistors that are about 13% slower than those produced in the 28 HPL and 28 HP processes (for the types of transistors Xilinx would be using to build its Series-7 FPGAs) while exhibiting more than twice the leakage, also according to the Xilinx White Paper. The advantage of the 28 LP process is that it’s less expensive.

Eliminating the 28 LP process as a possibility left the choice between TSMC’s 28 HPL and 28 HP processes. Both processes can produce equally fast transistors but the 28 HP process produces transistors with about twice the leakage of the 28 HPL process for the types of transistors Xilinx would be using to build its Series-7 FPGAs. According to the White Paper, TSMC’s 28 HP process is better suited to GPU and CPU designs that require the ultimate performance and that have the power budget (~100W) to achieve that performance. The Xilinx Series-7 FPGA power budget is 40W, so the company selected TSMC’s 28 HPL process technology.

Does that mean that the TSMC 28 HPL process technology is the “best” for every design? Certainly not. The terrific thing about the Xilinx White Paper is how deeply it delves into the thinking behind the selection. If they read the White Paper, your Silicon Realization team members will also be able to replicate those thought processes and make the right selection for your design.

Note: The first blog entry in this series on the Xilinx 28nm low-power SoC design White Paper was “3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you’re not designing FPGAs!


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Silicon Realization, SoC Realization, System Realization and tagged , , , . Bookmark the permalink.

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