3D Thursday: Produce cost-effective 2.5D and 3D devices. Attend the Known Good Die conference, November 15

Robert Patti, Chief Technical Officer and VP of Design Engineering at Tezzaron Semiconductor is the just-announced speaker at the Known Good Die conference being held on November 15 in Santa Clara, CA. His topic: Using Repair & Redundancy with KGD to Produce Cost Effective 2.5 and 3D Devices. Of course, you don’t build 2.5D or 3D IC assemblies without known good die, so this conference is a natural for anyone involved in 3D ICs. This conference will give you an up-to-date view of the industry trends in 2.5D and 3D IC assembly. Experts will outline the KGD capabilities and plans of key supply-chain vendors. Also, 3D IC supply-chain customers will highlight their KGD requirements as well as highlight the major benefits that 2.5D and 3D ICs deliver to them.

The technical sessions include:

  • 3D TSV (through-silicon via) applications
  • Design, manufacturing, and test of 2.5D and 3D stacks using KGD
  • Testing for perfection
  • Do known good die constitute a barrier to 3D commercialization (a panel discussion)

Register here.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 2.5D, 3D, EDA360, Silicon Realization and tagged , , , . Bookmark the permalink.

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