3D Thursday: Boosting the bandwidth of Wide I/O SDRAM to 1 Tbit/sec through standards evolution

This week’s DesignCon included a panel on 3D standards. You can read a review of the panel here in EETimes. Many topics were discussed, but the nugget I want to focus on in this blog post is the issue of Wide I/O SDRAM. The JEDEC Wide I/O SDRAM spec (JESD229) calls for a 512-bit-wide data interface (split into four independent 128-bit channels) running at 266MHz with one transfer per clock cycle (single data rate signaling). This spec was created specifically for the low-power needs of mobile applications such as mobile phone handsets, where the total amount of energy available from a charged battery drives nearly all design decisions. (See “3D Week: JEDEC Wide I/O Memory spec cleared for use”)

It’s clear that the initial Wide I/O specification with its peak bandwidth of 4.26 Gbytes/sec/channel will not satisfy all bandwidth requirements for all future systems. One would not expect that. So 3D memory standards are in the cards and according to Liam Madden, the corporate VP at Xilinx in charge of that company’s 2.5D FPGA efforts, next-generation Wide I/O JEDEC standards are in the works that target Tbit/sec data rates for high-performance requirements. These new standards will also explicitly support 2.5D and 3D memory stacks.

Note: The Electronic Design Process Symposium being held in Monterey will devote an entire day to 3D IC manufacturing and assembly topics. That day is April 6. You can find out more about the event here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization and tagged , , , , . Bookmark the permalink.

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