3D Week: JEDEC Wide I/O Memory spec cleared for use

According to Ken Shoemaker, Vice-Chair of the JEDEC 42.6 Low Power Memories committee, the Wide I/O specification has been finalized and approved by the directors. It will be published shortly. Participants in the effort included representatives from Elpida, Hynix, Micron, Qualcomm, TI, Intel, AMD, and Apple (and more but I couldn’t write them down fast enough).

Shoemaker spoke at this week’s GSA 3D IC Working Group meeting held at an Applied Materials facility in Silicon Valley. The objective of the Wide I/O standard effort was to develop a high-bandwidth SDRAM interface specification that delivers twice the memory bandwidth at the same I/O power as the existing LPDDR2 specification. In addition, the Wide I/O specification allows for thinner and smaller memory subsystem form factors through the use of TSVs (through silicon vias), which permit 3D stacking of bare memory die. (Goodbye DIMMs and POPs.)

The final Wide I/O specification calls for a 512-bit memory interface, broken into four independent channels (A through D), each channel operating at clock speeds to 266 MHz using SDR (single data rate) signaling. This results in an aggregate bandwidth of 17 Gbytes/sec for Wide I/O SDRAMs (4.26 Gbytes/sec/channel). The specification supports as many as four memory banks per channel, which permits die stacking of as many as four Wide I/O SDRAM die. The specification also calls for 1.2V signal levels. Shoemaker said that the 1.2V level was chosen because it is the lowest standardized signaling voltage currently supported by memory vendors.

The Wide I/O specification employs “LPDDR2-like” commands and timing parameters.

Work on a successor to the Wide I/O SDRAM specification has already started according to Shoemaker. The new objective is to deliver a specification with as much as eight times the performance of the newly minted Wide I/O specification and with explicit support for 2.5D assembly. There was no explicit requirement for 2.5D support in the original Wide I/O effort, although it is possible to use SDRAMs manufactured to the Wide I/O specifications in 2.5D assemblies.

See Richard Goering’s analysis of this development in his Industry Insights blog. Click here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, SoC Realization, System Realization, Wide I/O. Bookmark the permalink.

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