Just how high is the 20nm design mountain of challenges?

One of the last presentations at last week’s Global Technology Conference was the talk on 20nm design challenges presented by Wei Lii Tan of Cadence. Tan first summarized the benefits of the 20nm process node relative to 28nm:

  • 30-50% better performance
  • 50% area reduction
  • ~30% switching power savings

These desirable attributes will attract design teams working on a variety of applications including mobile computing, servers, smartphones, entertainment systems, and wireless equipment.

But 20nm performance doesn’t come for free. A lot of effort from the foundries, from EDA vendors, and from Realization teams will be needed to climb the 20nm mountain. For example said Tan, there are more than 400 new advanced layout rules needed for 20nm design. Further, 20nm designs must employ double patterning on critical layers. This is a new situation and the need for double patterning introduces an entirely new set of design rules.

The clear need here—from an EDA perspective—is to go far beyond design rule checking (DRC) and deeply into more extensive design-for-manufacturing (DFM) techniques. As discussed previously in this blog (see “Who else wants to see a 60x speedup in DFM signoff on a 28nm design?”), this transition from DRC to DFM is already taking place at the 28nm process node and will intensify at 20nm. GLOBALFOUNDRIES calls this enhanced methodology DRC+ because it is far more than DRC.

Although it has often looked like double patterning was needed to realize previous IC process generations, lithographic advances have held off the need for the technology—until now. Double patterning is required and it is being adopted by the IC foundries for 20nm designs because we are finally reaching the very limits of optical lithography using 193nm argon-fluoride laser light. Double patterning doubles wire pitch by permitting wires on alternating tracks to be printed separately. Without double patterning we cannot achieve the densest metal pitch possible at the 20nm process node. The following image should help.

Although 20nm lithography can print wires thin enough, it cannot space the wires closely without double patterning, which is a must for wire pitches of less than 80nm. Note: Cadence published a detailed paper on “Double Patterning Compliant Logic Design”  with GLOBALFOUNDRIES and Applied Materials earlier this year at the SPIE Advanced Lithography Conference.

However, EDA tools must work differently to accommodate double patterning, starting with new requirements in placement and routing. Cadence has implemented double-patterning-aware placement and a new correct-by-construction routing algorithm called FlexColor to accommodate the needs of double patterning. Double-patterning-aware placement must take cell density and manufacturability into account in addition to minimizing wire length. The correct-by-construction FlexColor routing approach improves area efficiency (saves silicon) and makes ECOs easier to accommodate. One key consideration here is that placement, routing, and accommodating ECOs must be as automatic as possible because of the design complexity at the 20nm node.

Timing variability will also present new design challenges at 20nm because the 20nm wires are thinner and longer, which results in increased coupling between wires and additional signal-integrity problems. Realization teams will need to perform even more parasitic extraction and modeling to combat these design problems.

Another challenge, one that’s pretty obvious and already mentioned two paragraphs above, is that the 20nm process node permits even bigger, more complex designs. Like an iceberg, this simple statement hides a lot of associated design methodology changes and challenges. Ever more complex chip designs demand even more abstraction in the form of more design IP use and reuse, which in turn places even more emphasis on IP readiness and the reliability of IP sources. In addition, complex SoC designs cannot afford to run everything on the chip at the same time because they will dissipate too much power—and likely don’t need to. Large systems often do not exercise all subsystems at the same time.

Consequently, there’s an increased need for more power management an better power-management techniques and methodologies with 20nm designs and these power-management requirements stretch across the silicon, package, and board-level Realizations. In turn, said Tan, these issues are causing and continue to cause an explosion in verification requirements, which in turn will force the development of entirely new verification strategies to correspond to the additional abstraction levels needed merely to tackle such large designs.

Cadence has been working with other vendors to provide early access to 20nm design tools. For example, Samsung and Cadence announced the tapeout of a 20nm test chip incorporating an ARM Cortex-M0 processor back in July (see “Samsung 20nm test chip includes ARM Cortex-M0 processor core. How many will fit on the head of a pin?”). There have been multiple tapeouts of 20nm chips using Cadence tools to date said Tan, and there are more in progress.

Be sure to download a free copy of the Cadence 20nm White Paper. Click here.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in ARM, EDA360, Globalfoundries, Silicon Realization, SoC Realization and tagged , . Bookmark the permalink.

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