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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- Asynchronous FIFO design disaster forces silicon respin. A cautionary SoC design tale from the trenches.
- What about the Denali Party? The big question for DAC 2011 is now answered.
- Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP
- Vizio (!) introduces line of high-end Windows PCs and notebooks. Didn’t they didn’t read that “post-PC” memo?
- New Mixed-Signal Methodology Guide provides design, verification and implementation methodologies for advanced mixed-signal designs
- Friday Video: SpaceShipTwo is a perfect example of a way to “Think Different” for System and SoC Realization teams
- Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?
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Tag Archives: GDDR5
Zowie! More than 50 x86 cores on the Intel Knights Corner Manycore Coprocessor
Today at the Hot Chips 24 conference, George Chrysos discussed the Intel MIC (Many Integrated Core) architecture of the Knights Bridge chip, to be formally called the Intel Xeon Phi coprocessor. This chip runs Linux, but it’s designed to act … Continue reading
Posted in EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged GDDR5, Intel, Knights Bridge, Manycore, Phi, Xeon
2 Comments
What would you do with a 23,000-simultaneous-thread school of piranha?…asks NVIDIA
Last night, Michael Shebanow took members of the local IEEE Computer Society deep into the world of graphics processing and graphics processing units (GPUs). Over an hour and a half, he revealed some interesting and surprising facets to the topic. … Continue reading
Posted in EDA360, Silicon Realization, SoC Realization, System Realization
Tagged AMD, DDR, Fermi, GDDR5, Nvidia
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