I’ve been discussing Gregg Bartlett’s talk at this week’s Global Technology Conference and thought I’d focus this blog post on one graphic:
As I mentioned in my last post, “GLOBALFOUNDRIES’ 28nm process comes in three flavors. Which is right for you?”, Bartlett indicated that there would only be one major flavor for GLOBALFOUNDRIES’ 20nm process technology—20nm-LPM (low-power manufacturing). The graph above surely shows why. GLOBALFOUNDRIES expects that the 20nm-LPM process technology will yield circuits that are 35% faster than circuits in the company’s 28nm-SLP (super low power) process technology—at the same leakage levels—and 25% faster than the company’s 28nm-HP (high-performance) process technology—again at the same leakage levels. If that’s not fast enough, then there will be a 20nm-SHP (super high-performance) process technology that gives you another 10% speed boost. GLOBALFOUNDRIES expects the 20nm-LPM process technology to be available in 2013 and the 20nm-SHP process technology to be available in 2014.
Note: To get a jump on 20nm chip design, see the new Cadence White Paper on 20nm design. Click here.
EDA360 Insider 
This is confusing. The graph shows 20SHP as having substantially lower leakage than any of the other processes – regardless of the speed specification. This does not accord with my layman’s (mis?)interpretation of the term “low-power manufacturing”; help – please?
George, I do not see how you get this interpretation. The curves all track on relative leakage. If you mean substantially lower leakage per GHz, then yes, the curves do seem to show that. The only hint that Bartlett gave in his talk is to say that the 20nm process technology would have transistors with four different Vts and multiple gate lengths, so that the most appropriate transistor could be chosed in all places. Beyond that, you’d have to ask GLOBALFOUNDRIES because it’s their presentation.