Agilent knocks one out of the park with new, low-cost line of digital scopes—a very competitive entry into the low-end DSO market and a perfect example of EDA360 design using end-to-end design and apps.

Today, in the middle of the announcement onslaught from wireless communications vendors coming out of the Mobile World Congress (MWC) in Barcelona, Agilent rolled out a blockbuster announcement of its own that’s not part of the MWC milieu: the InfiniiVision 2000 and 3000 X-Series of low-end, digital sampling oscilloscopes (DSOs).  There are no fewer than 26 DSO models in these two new Agilent DSO families, selling for $1230 to $11,590. That’s a huge product range covering a broad set of features that sells for a wide range of prices, all based essentially on one hardware DSO platform. Now EDA360 Insider isn’t a blog about DSOs, but it’s very much a blog about the design of electronic products and Agilent’s marketing team has done such a good job of getting coverage for this announcement that we can get an excellent feel for how this product was designed to compete nose to nose with established vendors in the low-end DSO space, where Agilent admits it had not had much of a presence.

Until now.

First, a bit of history about Agilent and DSOs. It’s a personal history because I was there at the time. Back in the 1970s when Agilent was still part of HP, I was a design engineer in HP’s Desktop Computer Division. HP kept design engineers well equipped with test equipment—HP test equipment. And that included analog oscilloscopes (because DSOs hadn’t been invented, yet). Back then, HP’s Colorado Springs Division designed and built HP’s analog scopes. To put it mildly, the analog scopes just weren’t competitive. As has happened several times in HP history, the Colorado Springs Division reinvented itself as a DSO vendor and quickly went from follower to leader.  Agilent inherited that mantle.

Next, you need to know that Agilent has had a consistent DSO core architecture since 1996. It’s called “MegaZoom” and it’s based on the idea of always-on, deep memory. That means that a MegaZoom DSO needs a lot of memory and the higher the DSO’s sample rate, the more memory these Agilent MegaZoom DSOs need. So it might seem like a dilemma, reconciling the need for large, fast, deep memory while trying to build a competitive, low-end DSO. What do you do to resolve this dilemma?

The answer: hit the problem with a big technology stick.

Agilent’s InfiniiVision 2000 and 3000 X-Series of low-end DSOs employ a 4^th-generation of MegaZoom, MegaZoom IV, embodied in a 90nm SOC. (See the block diagram below, derived from an EETimes article covering the announcement.) There are some 6M gates on this SOC—not a lot these days—but more important, the MegaZoom IV SOC incorporates 40Mbits of embedded, on-chip DRAM. (See “Agilent addresses economy oscilloscope sector in ‘significant launch’”) Normally, on-chip DRAM is less attractive than DRAM packaged in standard RAM chips because of cost. However, the Agilent DSO’s need high-speed access to the relatively small (using PC-scale RAM measurements) sample acquisition memory. (Note: See the associated data rates in yellow on the block diagram below.) When you need high-speed access to DRAM, you generally want an unusually wide interface to keep the memory-transfer clock rate reasonable, especially if you’re working with 90nm silicon. The best way to get a wide, high-bandwidth DRAM interface is to put the DRAM on the same piece of silicon as the acquisition circuitry so all the memory I/O is on chip. That’s precisely what Agilent’s engineers did.

This discussion and the above block diagram lead directly into a discussion of the overall system design of these Agilent InfiniiVision 2000 and 3000 X-Series DSOs. Now the EETimes article doesn’t carry details of the instruments’ system design but fortunately, Agilent had the foresight to loan an instrument to EE Video blogger (www.eevblog.com) David Jones in Australia. David loves to review test equipment, including DSOs, and David did what he always does: he pulled the Agilent DSO apart screw by screw (and there are a lot of screws) and he describes the design of the instrument in tremendous detail with a 17-minute video. Here’s the video:

David’s contribution to understanding the system-, SOC-, and silicon-level design aspects of Agilent’s InfiniiVision 2000 and 3000 X-Series DSOs is huge. Pay close attention to David’s description of the main board in the video. You’ll see that the analog channels run from the instrument’s input jacks to the heat-sinked A/D converter chip and to the Agilent MegaZoom IV SOC using serpentine differential traces. The serpentines ensure that all four analog signals reach the measurement chips in time sync with each other to permit simultaneous signal sampling.

You can bet that the board-level designers, the package designers, and the chip designers on this project had more than a few discussions to ensure that the timing budget was properly distributed among the three domains. This is an example of a fundamental component of the EDA360 design style. It’s called design intent. Now design intent has always been around, in ad hoc form. Engineers have used paper documents, electronic word-processing documents, and spreadsheets to keep track of the many forms of design intent. The EDA360 take on design intent is that it’s much better for the actual design tools to carry this design intent information in a design database along with the other design data. This is also an example of what Cadence means when it talks about end-to-end design: from chips to packages to boards. We can’t divine how the Agilent engineers shared design intent on this DSO project, but we can be sure that they did.

You should also note the use of a standard microprocessor, the STMicroelectronics SPEAr600 with two ARM9 processor cores, in these new Agilent DSOs. It’s discussed in David Jones’ video and appears on the block diagram above. Agilent’s engineers could have chosen to incorporate one or two ARM processor cores directly into the design of the MegaZoom IV SOC, but the system-level designers concluded that it was most advantageous to use a standard processor IC from a major commercial chip vendor. There could be many reasons for making such a choice including overall system cost, platform design and software considerations, familiarity with an existing processor IC, etc. As with most engineering, there’s no one right answer to the system-level design problem. There is a spectrum of right answers. Your design style should permit you to freely select the right answer from the design spectrum based on an objective analysis of the design data, including design intent.

The Agilent InfiniiVision 2000 and 3000 X-Series DSOs exhibit another unusual aspect of the EDA360 design style: apps. Because these Agilent DSOs run a standard, full-featured OS—Windows CE—it’s much easier for Agilent software engineers to develop apps that can be purchased by DSO owners and downloaded into the DSO. Apps help a system vendor extend the revenue model and profitability of a product’s design. That concept is also part of the EDA360 design style and applies just as well to DSOs as it does to printers and mobile telephone handsets.

So if you were thinking that the ideas behind EDA360 were strictly for consumer electronics, or that they didn’t apply to your piece of the electronics market, this announcement from Agilent should put that impression to rest. The many facets of EDA360-style design apply equally well to any electronic product you can imagine. Agilent has just proved that.

Note: For another teardown showing the innards of the Agilent 3000 series DSO, click here.