In the ramp-up to CDNLive! India this week, ASIC- and chip-design house Open-Silicon announced today that it has successfully taped out a processor design that will run at 2.4GHz using the end-to-end Cadence Silicon Realization product line. “We have fine tuned the tools and found good results from synthesis through to tapeout. Cadence’s Silicon Realization technology has also been a key contributor to our ongoing efforts to increase our predictability and reliability, both of which are critical to the Open-Silicon custom silicon solution,” said Taher Madraswala, vice-president of engineering at Open-Silicon. If you consider taping out a processor design that will clock at more than 2.4GHz under typical conditions a “good” design, then this tapeout qualifies as “good.” If you think pushing silicon’s boundaries to 2.4 GHz to be “great,” then it is that too.
Cadence is taking a new approach to Silicon Realization with an end-to-end deterministic flow that concurrently optimizes an IC design’s function, electrical specifications, and physical requirements. From the Cadence perspective, a holistic approach to silicon design, verification, and implementation hinges on three critical requirements:
- Consistent representation of design and verification intent
- Accurate models and higher levels of abstraction
- Convergence of late-stage design/manufacturing data into the early phases of design
A chip-design flow that satisfies all three of these requirements is what design teams need to tackle today’s most pressing design challenges. Traditional EDA, at least the EDA that has evolved since the early 1990s when synthesis took hold, employs a “silo” approach to product development where point tools perform individual design tasks in isolation. The key word here is isolation. A sequential, disjointed flow that fails to pass design intent between tools and a flow that does not take advantage of multiple abstraction levels—using the most appropriate abstraction for any given tool—will seriously challenge productivity, predictability, and—ultimately—profitability.
At 130nm, statistics say that the likelihood of hitting performance targets with the first design is 96%. At 40nm, that number drops to 71%. And the expectation is that at 22nm, first-time success rates will drop to 33%. These are the shadows of the future, if things do not change. This is what “business as usual” can be expected to buy for you and your design team.
The Cadence concept of and end-to-end Silicon Realization flow is to allow design teams, like the processor design team at Open-Silicon, to complete an entire design using the Cadence integrated end-to-end design, implementation, and manufacturability signoff flow to achieve the desired project goals using a deterministic design methodology.