New memory models support system design for next year’s introduction of Everspin STT MRAMs

I’ve written a lot about magnetic RAM (MRAM) including some recent coverage of a terrific MRAM panel at the Flash Memory Summit. (See “The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit” and “Can the Magneticians finally succeed in getting MRAM launched as a viable, low-power ASIC NV memory?” on the Web site.) Although Everspin has been shipping MRAM products for years already, most of the world is waiting for the next big technological leap in magnetic memory: STT (spin-torque transfer) MRAM, which uses an entirely different write mechanism involving polarized electron spin as explained in the above blog posts. Fascinating stuff. It’s been talked about for years.

How real is STT MRAM?

Well, Everspin announced today that it has now added SOMA (Specification of Modeling Architecture) models to the Cadence for Verification IP Catalog for Everspin STT MRAM products scheduled to be introduced in 2012. That means System Realization and SoC Realization teams can start working on system designs that incorporate STT MRAM now and be ready when the actual parts appear next year. (The Everspin STT MRAM models and 6000 more SOMA memory models for RAM and Flash devices are available at


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in EDA360, Memory, Silicon Realization, SoC Realization, System Realization and tagged , , . Bookmark the permalink.

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