Fujitsu adopts Cadence Chip Planning System for worldwide microcontroller design. Why? “It helps us build better chips faster.” Want one?

Fujitsu is one of the world’s top 10 microcontroller vendors. To stay competitive in this crowded, $15 billion market (2011 estimate by Databeans), a microcontroller vendor must freshen its microcontroller offerings at a very rapid pace and any boost in design speed and first-pass silicon success constitutes a real competitive advantage. Today, Cadence announced that Fujitsu has adopted a custom-tailored version of the Cadence Chip Planning System for microcontroller development at all nine of its worldwide design centers. Why? “It helps us design better chips faster,” said Mutsuaki Kai, vice president of Environmental Technology Development and Products Engineering Division, Fujitsu Semiconductor Limited.

The Cadence Chip Planning System allows multiple geographically dispersed project teams to perform early chip planning using models of internal IP. (The internal IP can be supplemented with IP from the IP ecosystem on ChipEstimate.com.) A central server provides the teams with access to the internal IP models, which allows the chip-design teams to perform “what-if” estimations of die size, power consumption, performance, and total chip cost.

Using the capabilities of this system, dispersed design teams can:

• Estimate design size
• Estimate design power (dynamic and leakage)
• Compare size, power, and performance of multiple designs or design variations
• Estimate achievable performance for specific manufacturing processes with specific IP components
• Create and edit the design’s block diagram using drag & drop techniques for IP blocks, and graphical drawing tools for connectivity
• Edit the design’s floorplan to explore the impact of IP block movement and rotation on size, power, performance, and cost
• Create power profiles using various activity modes and times
• Easily enable advanced power management techniques including power shutoff, multi-supply/multi-voltage power systems, and clock gating while measuring the impact of these techniques on design size and power consumption

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