Today, Cadence introduced three critical IP components that support the Wide I/O memory interface. These components include a configurable memory controller, a Wide I/O PHY, and appropriate verification IP. You can read more about this announcement in Richard Goering’s “Industry Insider” blog here and you can see the announcement itself here.
There’s one thing to understand: although the Wide I/O memory interface isn’t specifically limited to 3D IC assembly with TSVs (through silicon vias), it makes the most sense when used with the massive I/O capabilities of 3D assembly. The Wide I/O interfaces moves 512 bits at a time to boost transfer rate while cutting transfer-rate frequency. The net result is much greater memory bandwidth with a concurrent reduction in the amount of power needed to effect the memory transfers. “Wider is better” as the decade-old Pontiac Grand Prix commercials said.
Also, see this EDA360 Insider post from February: “Samsung DRAM combines 3D TSVs and wide I/O to move 12.8 Gbytes/sec. Is this the 3D revolution?“
EDA360 Insider 