PCI Express takes on Apple/Intel Thunderbolt and 16 Gtransfers/sec at PCI SIG while PCIe Gen 3 starts to power up

Two articles from EETimes give an exciting picture for PCI Express’ short- and long-term future. On the most immediate front, 23 adapter cards and 19 systems from PC and peripheral makers participated in the most recent PCIe Gen 3 plugfests. These are prototypes so it’s still early days for this interface standard, which moves data at 8 Gtransfers/sec. There are still many more chips, boards and systems to be designed using the PCIe Gen 3 standard. One of the two articles quotes Ramin Neshanti, chairman of the PCI SIG‘s serial communications working group, as saying “PCI Express Gen 3 is more sophisticated in its electrical design [than past PCI SIG standards], so we are giving members more feedback on how they are doing” with their first products. (Just a side note: PCIe Gen 3 designs clearly benefit from thorough verification before silicon implementation. To do that, you need good verification IP.)

At the same time, you should not be surprised to hear that engineers working on PCIe are already thinking about PCIe Gen 4 and 16 Gtransfer/sec/lane. The same article quotes PCI SIG president Al Yanes: “The initial report we got yesterday is a PCI Express 4.0 is feasible–we have to work out the details, but it is feasible.” A group consisting of people from AMD, HP, IBM, and Intel are simulating at the chip, channel, packet, and socket levels and they have determined that they can push PCIe throughput over copper to at least 16 Gtransfer/sec—possibly more. Their final report on this feasibility study is due by the end of the year.

Finally, there’s the problem of moving data externally from box to box. The frontrunner here is the recently announced Thunderbolt standard from Apple and Intel, which uses an optical cable to move 10 Gbps. (See this previous blog post from EDA360 InsiderWill Intel’s Thunderbolt alter the stakes in the I/O war between photons and electrons?“) Contrast that rate with the 4-lane external version of PCIe Gen 3, which would achieve transfer rates of 32 Gbps over copper at distances to 3m. The spec for this standard could be another year or so away according to the article.

For more information on PCIe Gen 4, see this EETimes article.

For more information on the external version of PCIe Gen 3, see this EETimes article.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Silicon Realization, SoC Realization, System Realization and tagged , , , , , , . Bookmark the permalink.

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