Friday Video + 3D Thursday: Xilinx Virtex-7 H580T uses 3D assembly to merge 28Gbps xceivers, FPGA fabric

The first 3D part in the Xilinx Virtex-7 FPGA family—the 2000T—permitted the construction of a huge FPGA while sidestepping the yield issues of large 28nm die. Now, Xilinx has used 3D IC assembly to meld two FPGA logic slices and a high-Gbps multi-transceiver die into another part: the Virtex-7 H580T. The result is a 3D device with 870K logic cells, as many as sixteen 28Gbps serial transceivers, and as many as seventy two 13Gbps transceivers.

Here’s a graphic showing how the two FPGA logic slices and the transceiver die attach to the silicon interposer that acts as the substrate for the Xilinx Virtex-7 H580T.

And here’s a video that explains a lot of what’s going on in this product and how 3D IC assembly helps:

For more information on the Xilinx Virtex-7 2000T, see “Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W”

Friday Video: The DAC Zone from ChipEstimate

Re-imagining Rod Serling as Sean O’Kane of Chip Estimate and “The Twilight Zone” as “The DAC Zone.” This video is just too cute for words.

 

Friday Video: A short film for people who love making things of beauty

You’re too late to sign up for the DAC Denali party, unless you…

The Denali Party by Cadence takes place next Tuesday night at Ruby Skye. If you have not yet signed up for a wristband, you’re too late. Sorry. We’re more than full.

However, I’m here to tell you a secret that might—might—still get you in. If you are at the Cadence DAC booth (#1930) precisely at noon next Tuesday, we will be giving out all unclaimed wristbands, first come, first served.

The party starts at 8:30 pm. It’s at the Ruby Skye night club near Union Square in San Francisco. No one, not even me, gets in without a wristband.

Gary Smith was talking ESL more than 15 years ago. You can finally get on board at DAC next week

Take a look at this EETimes article by one-time editor Mike Santarini who joined EETimes 15 years ago when EDA’s top analyst Gary Smith was discussing ESL (Electronic System Level) design. Well, we’re still talking about it and things have progressed fairly far. We’re now into multiprocessor and multicore design and we now need ESL to get software development off the runway much earlier in the design cycle.

Want to see how far we’ve come? Want to hear some actual war stories from the pioneers who are blazing the trail? Want breakfast? All things are possible.

Next Tuesday at DAC, you have a chance to hear LSI Corp, AMD, and Cadence discuss “Addressing Hardware/Software Co-Development, System Integration, and Time to Market.” More info and registration here.

DAC 2012: Get answers to all of your EDA questions at 78 Cadence demo suite slots

Next week (Monday, Tuesday, and Wednesday) you can get all of your EDA questions answered at the Cadence DAC demo suites. There are 78 demos over the three days covering the following EDA topics:

• Mixed-signal and low-power design
• RTL-to-GDSII design flows
• Custom/analog IC design
• Functional verification
• Verification IP
• System development and HW/SW integration
• High-level synthesis
• Signoff analysis
• PCB and packaging

Click here for more information and to register for one of these 78 demos.

The EDA360 Insider is on vacation and will return on May 26, 2012

Beyond breakfast: An ethical bribe for attending “The Path to Yielding at 2(x)nm and Beyond” at DAC

Yesterday, I wrote about a terrific discussion panel about the challenges of 20nm design at DAC. I am moderating the panel and there will be speakers from the Common Platform partners including IBM, Samsung, GLOBALFOUNDRIES (just confirmed!), and Cadence. (See “The path to 20nm includes breakfast on Wednesday, June 6”.) Yes, it’s a morning panel, so we’re bribing you with breakfast. But now we have another ethical bribe to offer: a pocket toolkit. It’s got four flat-bladed screwdrivers and two Phillips screwdrivers in one handy kit. It looks like this:

Everyone attending the panel gets one of these babies. However, the room is already more than half full so you’d better register now. Sooner rather than later.

For more information, click here.

To register, click here.

There’s a solar eclipse coming. Here’s a test shot from a Canon 60D dSLR, a Spiratone 400mm Sharpshooter, and a 2x telextender.

The EDA360 Insider is going on vacation soon and will be dead center in the path of the solar eclipse on May 20. In preparation, I tried out my photo equipment today to see if I’ll be able to capture reasonable images of the sun. I’m using a very up-to-date 18Mpixel Canon 60D dSLR with a very, very old Spiratone 400mm Sharpshooter lens and a 2x telextender from eBay. There’s a 40-year gap between camera body and lens. The lens is manual focus, manual aperture, auto nothing. Nevertheless, you can see the sunspots.

AMD’s new Trinity APU (Accelerated Processing Unit) for laptops/notebooks is a poster child for IP-centric SoC design

Yesterday, AMD introduced its second generation of A-series APUs (Accelerated Processing Units) that combine two to four Piledriver x86 microprocessor cores—each with 2Mbytes of L2 cache memory—with a Radeon 7000 GPU (Graphics Processing Unit), an HD Media Accelerator, a display controller with HDMI port, a dual-channel DDR3 SDRAM controller, and 24 lanes of PCIe interconnect. Here’s a die photo/block diagram of the dual-core version:

AMD markets these APUs under the “Fusion” and “Vision” brands and the AMD press release for the new APU series lists five members: two have two x86 processor cores and three have four processor cores. According to AMD, this sort integration will allow laptop/notebook vendors to build products that sell for as little as $500 with as much as 12 hours of battery life.

From a design perspective, the new A-series AMD APUs illustrate the way SoCs are now being designed. The die photo clearly shows an assembly of IP blocks including the Piledriver x86 processor cores, the associated L2 memory caches, the GPU, HD Media accelerator, DDR3 SDRAM controllers, and the PCIe I/O blocks. Using a calibrated eyeball, these identifiable IP blocks appear to consume more than 80% of the device.

To see the complete AMD slide deck on the announcement, click here.