Friday Video: Robot does Travolta? Ah, Ah, Ah, Ah, Stayin’ Alive

This short video shows an anthropomorphic robot named PETMAN, a DARPA project from Boston Dynamics, with a soundtrack added by a YouTube user. Fun!

By the way, I saw a preview of the movie “Robot and Frank” last weekend. Also fun. See it when it rolls into your town.

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Workshop on Analog and Mixed-Signal Design Automation: November 8 in Silicon Valley

A 1-day workshop on Analog and Mixed-Signal Design Automation will be held on November 8 in conjunction with ICCAD in Silicon Valley. It’s no secret that advanced-node process scaling makes all IC design more complex and more challenging—even more so for analog and mixed-signal designs. This workshop will cover the latest design automation advances specifically for analog and mixed-signal IC design teams. Click here for more info.

And just as a reminder, Cadence has just published a brand new book on mixed-signal design and verification methodology. You have a week left before the introductory price disappears, so this would be a really good time to purchase your copy. I’m told it’s an excellent book. Click here to download a free PDF copy of the book’s first chapter.


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3D Thursday will return next week

This week is being consumed by the Flash Memory Summit. 3D Thursday will return next week. Thanks for standing by.

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Nikon announces Android-powered camera: the $349 Coolpix S800c

Nikon Coolpix S800c Android-powered camera

Nikon has just announced an Android-powered point-and-shoot camera—the $349 Coolpix S800c. It’s a 16Mpixel camera with a 10x optical zoom but the real innovation appears on the back in the form of a touch-panel LCD 0.8Mpixel OLED display that is immediately recognizable by anyone who has every owned a smartphone. The Nikon Coolpix S800c runs Google’s Android 2.3 (Gingerbread) and has a built-in WiFi connection so that images taken with the new camera can be easily uploaded to the Web. Now I’m not a big image and video uploader (wrong demographic) but Nikon is specifically targeting this camera at consumers who regularly use online services such as Facebook and Instagram. In fact, the video on this announcement page repeatedly underscores the camera’s use as an instrument of social media interaction.

Nikon’s Coolpix S800c camera runs the Google Android operating system and GUI

This new Nikon camera is an excellent example of how embedded systems are migrating to 32-bit processors (including the ARM Cortex-A9 processor reported to be in this camera) and large, standard operating systems and GUIs such as Google’s Android. With that migration, embedded systems are also using far more RAM and ROM (or Flash) than ever before—the Coolpix S800c is reported to contain 512Mbytes of RAM and 4Gbytes of NAND Flash memory—which is precisely why Micron Technology’s VP of Embedded Marketing Jeff Bader brought this new camera to my attention today at the Flash Memory Summit.

The Nikon Coolpix S800c is not just a camera. It’s a portable device with a WiFi connection to the Internet that’s able to run many of the 500,000 Android apps that are on the market. Not aimed at my age bracket perhaps, but an important feature to many potential camera buyers.

It’s appropriate to ask why anyone would need an Android-based point-and-shoot camera when there’s already one built into every smartphone. Nikon’s video, mentioned above, addresses that question directly. The Coolpix S800c camera’s optics, imaging sensor, exposure control, fill flash, and shutter responsiveness are all vastly superior to the corresponding elements in a smartphone. It’s easier to take better photos—in most cases much better photos—with the camera than with a smartphone. For people who care about image quality, those better images could make the difference. For others, the idea of carrying a second device to replicate the image-making ability of their phone won’t make sense. Different strokes, and all that.

Micron’s Bader asserts, and I agree, that embedded products such as the new Nikon coolpix S800c will become increasingly common as consumers first become accustomed to and then will expect advanced touch interfaces on all of the electronic products that they purchase. Their buying habits are being shaped by high-end products from successful systems companies including Apple, Google, and Samsung. Others will need to follow, or risk being perceived as old-fashioned, outmoded, and—even worse—obsolete.

Posted in Android, ARM, Cortex-A9, EDA360, Linux, Mobile, System Realization | Tagged , , , , , , , | 2 Comments

How Skyera developed the 44Tbyte, enterprise-class Skyhawk SSD from the ground up. A System Realization story.

I rarely get to tell an in-depth System Realization story like this one. The development of the 44Tbyte, enterprise-class Skyhawk SSD starts with a clear picture of the objective—build an enterprise-class, solid-state storage server using commercial MLC (multi-level cell) NAND Flash memory—and unfolds, well, systematically from there. I heard this story yesterday during a private meeting with Skyera’s CEO, Rado (Radoslav) Danilak, and VP of Product Management Alessandro Fin at the Flash Memory Summit in Silicon Valley.

The choice of commercial-grade MLC NAND Flash is eminently sensible in this application once you look at this photo that I shot of the Skyhawk SSD during the meeting:

Skyera Skyhawk SSD, a 44Tbyte enterprise-class storage peripheral

Fitting 44Tbytes of NAND Flash into that 1U, half-depth, rack-mount box calls for high density circuitry. The desire to sell the box at a low price for enterprise-class storage (see below) also drove the decision to adopt MLC NAND Flash memory for the SSD’s design.

However, there’s a very good reason why few enterprise-class SSD vendors use MLC NAND Flash memory in their products: raw MLC NAND Flash memory isn’t as durable as SLC (single-level cell) Flash and data integrity is paramount in enterprise-class storage applications. MLC NAND Flash memory is typically rated at 3000 P/E (program/erase) cycles while enterprise-class storage requirements demand on the order of 100K P/E cycles to achieve a 5-year product life. Most MLC NAND Flash is designed for use in USB drives and SD cards where durability is not the issue—cost and density are. Yet it was the relatively low cost and high density of MLC NAND Flash that drew Skyera to this type of memory for an enterprise-class storage peripheral.

Skyera decided that the way to extract enterprise-class performance and durability from MLC NAND Flash memory was to develop its own Flash-management algorithms. That decision led to the development of a proprietary NAND Flash controller for the Skyhawk SSD. The NAND Flash controller addresses write amplification, one of the biggest problems with SSDs based on NAND Flash memory. The additional P/E cycles caused by write amplification exacerbate the issue of limited MLC NAND Flash durability.

Another way to extend the durability of the MLC NAND Flash memory is to build in additional memory redundancy through RAID storage technology. However, Skyera looked at existing RAID algorithms from “leading suppliers” and discovered that these algorithms are all tailored for rotating storage media. Existing RAID algorithms have baked-in assumptions based on the interface, speed, and latency characteristics of hard disks and these existing RAID algorithms were not able to exploit the fine-grained nature of NAND Flash memory.

So Skyera developed its own RAID algorithms, which it calls RAID-SE. (The “SE” is for Skyera). The RAID-SE algorithms also went into the NAND Flash controller. These algorithms achieve RAID 6 reliability while reducing write amplification to extremely low levels.

One more technology went into the Skyera NAND Flash controller: compression. Data compression boosts SSD capacity and increases performance by reducing the amount of data traffic going into and coming out of the NAND Flash memory. Skyera developed its own compression algorithm tailored for the specific needs of enterprise-class SSD storage and implemented the algorithm in controller hardware because a software implementation wasn’t fast enough.

(Note: For an in-depth discussion of data compression and I/O bandwidth, see “Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? Does it matter?” in the Denali Memory Report.)

At this point, Skyera had a fast (high IOPS), high-capacity SSD based on commercial MLC NAND Flash memory. Using this SSD in a system presented the next bottleneck. The SSD could support a lot of storage traffic from multiple servers and the Ethernet ports linking the SSD to the enterprise system became a bottleneck so Skyera developed its own Ethernet switch and integrated it into the Skyhawk SSD design. The Skyhawk SSD’s proprietary Ethernet switch has forty 1Gbps and three 10Gbps Ethernet ports and it’s incorporated into the same 1U, half-depth box as the SSD appearing in the photo above. More important, the Ethernet switch is integrated into the SSD’s system design, which further boosts overall performance through some additional system optimization.

Skyera is selling the Skyhawk SSD for “under $3 per gigabyte – before compression and deduplication.” According to Danilak and Fin, if you compare that price with the cost of a RAID-based, enterprise-class, hard-disk storage system with a comparable network switch, you will find the price to be more than competitive. Skyera achieved this price/performance breakthrough using a systematic approach to System Realization, starting with the adoption of MLC NAND Flash (the underlying premise that makes the Skyhawk SSD cost-competitive with rotating storage), the development of the NAND Flash controller and the RAID-SE algorithm to overcome the limitations of MLC NAND Flash memory, and finally the addition of sufficient Ethernet throughput to unleash the Skyhawk SSD’s system potential.

This story plots the methodical analysis of a well-defined system problem and a step-by-step development of hardware and software to overcome the challenges presented by the problem. It’s a terrific lesson in effective System Realization and I’m indebted to Rado Danilak and Alessandro Fin for sharing the story with the EDA360 Insider.

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Raspberry Pi + Canon = Camera Pi: ARM 11 and Linux hack of a Canon 5D Mk II DSLR

Here’s a link to a very interesting and cool hack of a Canon 5D Mk II DSLR achieved by stuffing a Raspberry Pi Linux-based single-board computer into an accessory battery grip. EDA360 Insider has covered the Raspberry Pi board before. (See “3D Thursday: Raspberry Pi Foundation’s $25 ARM board boots Linux using stacked DRAM.”) The board is a Linux platform based on a 700MHz ARM 11 processor core running in a Broadcom Mobile Multimedia Processor SoC. It attaches 128 or 256 Mbytes of SDRAM on top of the Broadcom SoC using POP (package-on-package) 3D assembly. Significantly, it sells for about $25!

Photographer David Hunt says he had the idea to couple a single-board computer to the Canon 5D Mk II DSLR for “a couple of years” and that the Raspberry Pi’s specifications triggered his desire. He took action. Using an old, broken battery grip, Hunt installed the Raspberry Pi board into the space formerly occupied by two batteries in the grip.

The Raspberry Pi communicates with the camera via a USB port (the Raspberry Pi is the host in this case). It can download the images via USB and then transmit the images via WiFi or Ethernet. In later updates, Hunt notes that he’s now got the Raspberry Pi clicking the shutter on the camera.

Here’s a video of the whole thing in action:

For more information, see Hunt’s August 13 blog post, “Camera Pi—DSLR Camera with Embedded Computer,” where you’ll find detailed images of this ingenious hack.

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Daniel Nenni at SemiWiki publishes a [very] brief history of the SoC

Daniel Nenni has just posted a very brief history of the SoC, with heavy emphasis on SoCs for mobile products. The emphasis is probably warranted because mobile designs really have driven SoC design for the past decade. One of the best things about this short history, in my opinion, is the set of links to SemiWiki descriptions of mobile SoCs including:

  • Apple A5X
  • NVIDIA Tegra 3
  • TI OMAP4
  • QCOM Snapdragon S4
  • Samsung Exynos

Click here to see Nenni’s SoC post.

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Which Android Phones are winning in Asia, and where?

This is too cool! Animoca publishes games for Android-based platforms and, apparently, collects information about what type of platform a game is downloaded into. So the company just published an analysis titled “Animoca data: the top Android phones in key Asian markets for July 2012” and this graphic, which answers the question in immense detail including handset vendor and specific phone models.

There’s a wealth of platform data available on this site.

Thanks to Dean Takahashi for the pointer!

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Friday Video: Mars Rover video goes viral—We’re NASA and We Know it

Hip Hop and NASA? Whoda’ thunk it? Some fevered brain saw the connection between NASA and LMFAO.

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Friday Video: A brief history of PDAs with system-design tips through three teardowns

Once more, Australia’s Dave Jones has produces an eminently watchable and helpful video where he tears down three PDAs from 1986, 1996, and 2004: A Psion Organiser, a US Robotics Palm Pilot 5000, and an HP iPaq. Over two decades, processor speeds jumped from 3.6864MHz to 16MHz to 400MHz; RAM jumps from 8 Kbytes to 512 Kbytes, to 128 Mbytes (!); and the processors go from the Hitachi (now Renesas) 8-bit 6303 to the Motorola (now Freescale) 16/32-bit 68328 to the ARM-based Intel 32-bit Xscale PXA255. (Yes, Intel once manufactured ARM processors—and not that long ago!) Construction ranges from through-hole to SMT. The Psion PDA is old enough to pre-date the broad use of Flash memory, so its data is stored in battery-backed SRAM while the other two PDAs make heavy use of Flash memory.

This kind of product archaeology gives system designers a good grounding in ideas that worked (in their day) and stocks your personal design toolbox with much-needed ideas—what once worked, what doesn’t work any more, and what might still work. As usual, Jones’ observations ranging from pcb trace density to interboard connector schemes to design for testability, power conversion, and mechanical assembly. All of these topics are educationally invaluable.

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Friday [not quite a] Video: Slideshow of old Packard manufacturing plant set to music

The Packard Motor Company made automobiles in Detroit for decades and closed the doors of its manufacturing plant in 1958 after going bankrupt. Although the 95-building complex closed more than half a century ago, it’s still there (for now), decaying, captured in amber by photographer Elvin Wyly. The following slide show, set to music, evokes the feeling of a lost civilization—which is why photographer Camilo José Vergara has called Detroit the “American Acropolis.”

Packard Plant Slide Show by Elvin Wyly.

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Friday Video: A personal invitation to Memcon from Sanjay Srivastava

Want to know why you need to be at Memcon this year? Here’s Denali Software founder Sanjay Srivastava to tell you why:

Now go and sign up! It’s a free ticket and includes breakfast, lunch, and some goodies—not to mention the great information you’ll hear. Register by clicking here. Now.

Posted in Memory, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , | Leave a comment

TI Stellaris promo features ARM Cortex-M4F dev board for $4.99—or possibly free

You’ve got a little more than a month to sign up for a $4.99 TI Stellaris Launch Pad Dev board based on the ARM Cortex-M4F processor core. Register and you get on the list to purchase a board for $4.99 but 25 registrants get the board for free.

Key features of the TI Stellaris microcontrollers include:

  • IEEE754-compliant, single-precision floating-point capability at 80 MHz
  • SIMD instructions
  • As much as 256Kbytes of embedded flash memory and 32Kbytes of SRAM
  • Low-power modes including power-saving hibernate
  • As many as two 12-bit 1MSPS ADCs and 24 analog input channels of
  • As many as two CAN controllers
  • Optional full-speed USB 2.0 with device, host, and OTG
  • Advanced motion control capability, with as many as 16 motion control PWM outputs and two quadrature encoder interfaces
  • As many as eight UARTs, six I2C, ports, and four SPI/SSI ports

That’s a lot for a fiver.

Here’s the heavy-metal teaser video for the Stellaris Launch Pad dev board:

Register here.

Posted in ARM, Cortex-M4, Texas instruments | Tagged , , , | 1 Comment

Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges

A couple of days ago, I let you know that Cadence had just published a comprehensive book on mixed-signal SoC design and verification. The book’s title is the “Mixed-Signal Methodology Guide,” written by the top mixed-signal design experts from across the industry. The authors work at companies that are currently pushing the boundaries of mixed-signal SoC development including Boeing, Cadence, ClioSoft, and Qualcomm.

I also gave a pointer to a location on where you could read the book’s first chapter online. However, I didn’t think that was enough for the EDA360 Insider’s readers. So I requested and got a PDF of that chapter, which covers:

  • Mixed-Signal Verification
  • Behavioral Modeling
  • Low-Power Verification
  • Design for Test
  • Chip Planning
  • AMS IP Reuse
  • Full-Chip Signoff
  • Substrate Noise
  • IC/Package Co-Design
  • Design Collaboration and Data Management

You can download the PDF by clicking on this link: Mixed-Signal Methodology Book Chapter 1. No tricks. No registration. Just click on the link and get the PDF. Immediate gratification ‘R us.

I think you’ll want to read this first book chapter and then I hope you’ll order the book here where it’s currently on sale at 40% off!

As a reminder, here’s the list of book chapters:

Chapter 1: Mixed-Signal Design Trends and Challenges
Chapter 2: Overview of Mixed-Signal Design Methodologies
Chapter 3: AMS Behavioral Modeling
Chapter 4: Mixed-Signal Verification Methodology
Chapter 5: A Practical Methodology for Verifying RF Designs
Chapter 6: Event-Driven Time-Domain Behavioral Modeling of Phase-Locked Loops
Chapter 7: Verifying Digitally-Assisted Analog Designs
Chapter 8: Mixed-Signal Physical Implementation Methodology
Chapter 9: Electrically-Aware Design Methodologies for Advanced Process Nodes
Chapter 10: IC Package Co-Design for Mixed-Signal Systems
Chapter 11: Data Management for Mixed-Signal Designs

Posted in EDA360, Mixed Signal, Silicon Realization, SoC, SoC Realization, Verification | Tagged , , , , | Leave a comment

Samsung Exynos 5 Dual mobile processor features two 1.7GHz ARM Cortex-A15 processors, a WQXGA display controller, and two LPDDR3 controllers to feed ‘em

This past weekend, the Web was abuzz with last week’s unveiling of Samsung’s Exynos 5 Dual mobile processor. This SoC features two 1.7GHz ARM Cortex-A15 processors rather than the previous Exynos generation Dual mobile processor that incorporated two 1.4GHz ARM Cortex-A9 processor cores. Between the ARM Cortex-A15 processor’s additional clock rate and its improved instructions/clock figure of merit (1.5x better for integer processing and 2x better for floating-point processing), Samsung says that the Exynos 5 Dual mobile processor has twice the processing bandwidth of the previous generation.

However, these two leading-edge CPU cores are not the only significant feature of this new mobile processor chip. It also includes a controller for 2560×2048-pixel WQXGA displays (also known as the “Wide Quad Extended Graphics Array”). Worst case, a WQXDA display controller operating at 60 frames/sec and 24 bits/pixel requires 8 Gbytes/sec of memory bandwidth. However, that’s with the display controller getting the entire memory interface. As the Samsung Exynos 5 Dual White Paper points out, assuming the display controller “only” takes 80% of the memory bandwidth, the chip will need 10 Gbytes/sec of memory bandwidth and that’s giving the two ARM Cortex-A15 processors a mere 2 Gbytes/sec  of memory bandwidth to share.

Here’s a graph of display resolution versus memory bandwidth from the Samsung Exynos 5 Dual White Paper.

Consequently, the designers of the Exynos 5 Dual mobile processor added two 800MHz LPDDR3 memory controllers to the design. Together, these SDRAM controllers can generate a peak bandwidth of 12.8 Gbytes/sec of memory traffic between the Exynos 5 Dual mobile processor and the attached LPDDR3 1600 SDRAMs.

Here’s a block diagram of the Exynos 5 Dual mobile processor:

For more in-depth information on the ARM Cortex-A15 processor core, see:

Want some Top Secret ARM Cortex-A15 implementation info?

Would you like some ARM Cortex-A15 resources to peruse?

The WORD on ARM’s big.LITTLE Cortex-A15/A7 design philosophy from Jack Ganssle, a leading expert and consultant on embedded design and firmware development

Realizing the ARM Cortex-A15: What does the road to 2.5GHz look like?

Want to know the secrets of implementing an ARM Cortex-A15 in an advanced process node? Read on!

ARM Cortex-A15—does this processor IP core need a new category…Superstar IP?

To get your own copy of the Samsung Exynos 5 technical White Paper, click here.

(Note: This blog post originally appeared yesterday in the blog.)

Posted in Cortex-A15, EDA360, Samsung, Silicon Realization, SoC, SoC Realization | Tagged , , , , | Leave a comment

New Mixed-Signal Methodology Guide provides design, verification and implementation methodologies for advanced mixed-signal designs

Cadence has just published the “Mixed-Signal Methodology Guide,” which provides an overview of design, verification and implementation methodologies for advanced mixed-signal designs based on recommendations from the book’s co-authors—top mixed-signal design experts from across the industry including authors from Boeing, Cadence, ClioSoft, and Qualcomm. Circuit designers will find the book helpful in understanding the many facets of mixed-signal design and verification. For managers, the book provides an overview of modern mixed-signal methodologies to make it easier to understand and plan for investment in design capabilities and skills.

Here’s a chapter list:

Chapter 1: Mixed-Signal Design Trends and Challenges
Chapter 2: Overview of Mixed-Signal Design Methodologies
Chapter 3: AMS Behavioral Modeling
Chapter 4: Mixed-Signal Verification Methodology
Chapter 5: A Practical Methodology for Verifying RF Designs
Chapter 6: Event-Driven Time-Domain Behavioral Modeling of Phase-Locked Loops
Chapter 7: Verifying Digitally-Assisted Analog Designs
Chapter 8: Mixed-Signal Physical Implementation Methodology
Chapter 9: Electrically-Aware Design Methodologies for Advanced Process Nodes
Chapter 10: IC Package Co-Design for Mixed-Signal Systems
Chapter 11: Data Management for Mixed-Signal Designs

Click here to read the first chapter of the book.

For more information about the book including ordering info, click here.

Posted in Mixed Signal, Silicon Realization | Tagged | Leave a comment

Friday Video: Dr. Who, Season 7 Preview

If you don’t understand why this is here, don’t sweat it.

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Friday Video: First flight of NASA Morpheus VTOL lander ends quickly and badly

The first untethered flight of NASA’s Morpheus vertical takeoff and landing vehicle ended quickly and badly. And then Morpheus exploded. As explained by the person who posted the following video on YouTube, “It appears to have had a guidance failure.”

Note: If you’ve watched the movie “Forbidden Planet,” you probably know you should not name a project “Morpheus.”

Also Note: This is not the first time something like this has happened. Neil Armstrong had to eject from a runaway Lunar Lander trainer shortly before it crashed and burned back in the 1960s, as you can see from this Discovery Channel video at about the 2:30 mark.

Yes folks, it’s still rocket science. The difference? No software back in the 1960s. Just human piloting finesse.

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Looking for an introductory Verilog book? How’s $24.95 sound?

Bob Zeidman, founder and president of Zeidman Consulting, has just published the third edition of his book “Introduction to Verilog.” It was first published a dozen years ago and is based on the Verilog seminars that Zeidman has given at conferences around the world.. You can buy the hardcover for $495 (I hope it’s got a hand-tooled leather book jacket and a gold bookmark for that price) or the more reasonably priced paperback edition for $24.95.

If you want to get a sense of Zeidman’s writing style before acquiring the book, download an excerpt from the book here. Remember, this is an introductory book. If you don’t need it, perhaps you know someone who does.

You can get a look inside the book and order it at Amazon.

Posted in EDA360, Silicon Realization, SoC, SoC Realization, Verilog | Tagged , , , | Leave a comment

Xilinx takes Zynq to 11—or more precisely to 1GHz

In the satirical 1984 movie “This is Spinal Tap,” Nigel the guitarist explains why the volume controls on his Marshall amps go to 11 instead of 10 like everyone else’s amps: “If we need that extra push over the cliff,” we put it up to 11. Xilinx just did that with the clock rate of its Zynq-7000 family of processors with integrated FPGA fabrics. The two ARM Cortex-A9 processor cores in the 28nm Zynq-7000 parts were originally specified at 800MHz. Now, they go to 1GHz.

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Need to make an ARM Cortex-A9 processor core all it can be?

A new blog published today on the ARM Web site titled “How do you take an ARM POP up one more notch?” describes a very recent collaboration between ARM and Cadence to enhance the ARM POP IP, which helps any SoC design team maximize PPA (power, performance, area) results. ARM has offered its POP IP for a couple of years but this is the first time that the company has modified its POP IP for a specific EDA design flow.

The ARM POP IP discussed is specifically for an ARM Cortex-A9 processor core implemented in a TSMC 40nm process technology.

Not your specific processor core?

Not your chosen process technology?

Wait just a bit.

Note: For more info, see Richard Goering’s Industry Insights blog “ARM and Cadence Improve Cortex-A Power and Performance with Optimized Flow” and this article in EETimes by Peter Clarke.

Posted in 40nm, ARM, Cortex-A9, Silicon Realization, SoC, SoC Realization, TSMC | Tagged , , , , | Leave a comment

3D Thursday: Save the date. 3D Architectures for Semiconductor Integration and Packaging Conference on December 12-14

The 9th International 3-D Architectures for Semiconductor Integration and Packaging Conference and Exhibition will be held December 12 -14, 2012 at the Sofitel in Redwood City, CA. It’s run by RTI International.

More info here.

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If Aladdin’s Genie lived in a Computer-on-Module, it might look like the Gumstix Overo

One of the funniest lines in the 1992 animated Disney movie “Aladdin” is when the frenetic blue Genie, voiced by the incredible Robin Williams, describes his situation:

“PHENOMENAL COSMIC POWERS; Itty-bitty living space,”

referring to his life in a lamp.

The Gumstix Overo series of COM (computer-on-module) boards based on Texas Instruments’ OMAP Application Processors remind me a lot of the Genie’s situation and in fact, the one-liner product description of even evokes some of the same imagery (without the Williams flourish):

“The Overo series packs a lot of computing power in a tiny package.”

Overo COM board with I/O breakout board

So what do you get on a board the size of a stick of chewing gum that costs $115 to $229?

A TI OMAP35x processor with POP (package-on-package) SDRAM and NAND Flash memory, a Bluetooth/WiFi module, an SD Card socket/slot, and power management. The TI OMAP35x Application Processors are based on a 600MHz or 720MHz ARM Cortex-A8 processor core and includes a huge number of integrated peripheral devices. Here’s a block diagram:

The TI OMAP35x Application Processor family is a good example of an SoC originally developed for the mobile phone handset market that has significant application in other sorts of embedded markets. The Gumstix Overo COM boards are one means of making that processing power available to system designers in an easy-to-try form that can be tucked away inside of nearly any product.

Phenomenal cosmic powers, indeed.

Posted in ARM, Cortex-A8, SoC, SoC Realization, System Realization, Texas instruments | Tagged , , , , , , | Leave a comment

How many SSDs does it take to saturate PCIe Gen 3? Would you believe 16 drives?

It’s now possible to conduct some interesting performance tests on real PCIe Gen 3 products and the video below shows you a PCIe Gen 3 RAID card talking to 16 SSDs, which is the number of drives needed to saturate a setup based on an Intel Sandy Bridge processor and chip set. The result is 6600 Mbytes/sec of throughput—about 90% of the theoretical maximum. With tweaking, that number might go up to 95%. Just watch the video.

For information on the PCIe Gen 3 IP used in the creation of the Adaptec RAID SoC, click here.

Posted in EDA360, IP | Tagged , , , , , | Leave a comment

How to program all of those SoC processor cores? Answers from Jim Ready. Free event, September 18.

While we can stamp out processors galore on an advanced-node SoC, programming those processors is another matter entirely. Yet “multicore” and “many-core” SoC designs are the in-vogue approach to processing performance. How to solve this dilemma?

Get a glimpse of one approach from Jim Ready, who has been very active in embedded operating systems since developing the world’s first commercially viable RTOS—VRTX—and offering it through his company Ready Systems starting in 1980. Since then, Ready has stayed with the embedded OS market, most recently as founder of embedded Linux pioneer MontaVista Software. Ready is currently the Chief Technology Advisor for Software & Embedded Systems at Cadence.

On Tuesday, September 18, Ready will give a presentation titled “Beyond Virtualization: A Novel Software Architecture for Complex Multi-Core SoCs” to the IEEE-CNSV (Consultants’ Network of Silicon Valley). The event will be held at the KeyPoint Credit Union in Santa Clara, CA. The talk is free and you don’t even need to register. Just show up at 7 pm. The location is 2805 Bowers Ave, Santa Clara, CA.

This is a great opportunity to hear one of the most insightful experts on advanced embedded software that you’re likely to find. More information here.

Posted in EDA360, Multicore, System Realization | Tagged , , , , , , | Leave a comment